PC87413 datasheet(94/257 Pages) NSC

94 / 257 page

5.0 X-Bus Extension (Continued)

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Revision1.2

Memory Transactions. The 32-bit address received from the LPC bus is used to decode the different memory zones de-

scribed in Section 3.15.3 on page 76. The address is then translated to the X-Bus address, using the following rules:

User-Deﬁned Memory Zones (MEM 0 and MEM 1) and 386 Mode-Compatible BIOS Range: The 28 least signiﬁcant

address lines of the LPC address are used as the X-Bus input address. Figure 13 illustrates the mapping for this

zone.

Legacy and Extended Legacy BIOS Range: The 17 least signiﬁcant address lines (A16-0) of the LPC address are

routed as the 17 least signiﬁcant address signals of the X-Bus (XA16-0). The upper 11 X-Bus address lines are driv-

en to ‘1’. This shifts the addresses to the top of the X-Bus memory space (see Figure 14).

Figure 13. LPC-to-X-Bus Address Translation: 386 Mode-Compatible BIOS Range

Figure 14. LPC-to-X-Bus Address Translation: Legacy and Extended Legacy BIOS Ranges

LPC Bus Address

FFFF FFFFh

xFFF FFFFh

X-Bus Address

FFFC 0000h

xFFC 0000h

0000 0000h

LPC Bus Address

FFFF FFFFh

xFFF FFFFh

X-Bus Address

000F FFFFh

xFFE 0000h

0000 0000h

000F 0000h

000E FFFFh

000E 0000h

Legacy BIOS

Extended

Legacy BIOS

PC87413 Datenblatt(PDF) 94 Page - National Semiconductor (TI)