CC1020-RTR1 datasheet(27/95 Pages) TI1

27 / 95 page

[

]

xoscx

(ADC _ DIV 2 : 0

CC1020

www.ti.com

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

In receive mode the frequency must be programmed to be the LO frequency. Low side LO injection is

used, hence Equation 8.

fLO = fc – fIF

(11)

Where:

fIF is the IF frequency (ideally 307.2 kHz).

5.8.1

Dithering

Spurious signals will occur at certain frequencies depending on the division ratios in the PLL. To reduce

the strength of these spurs, a common technique is to use a dithering signal in the control of the frequency

dividers. Dithering is activated by setting the DITHER bit in the FREQ_0 registers. It is recommended to

use the dithering in order to achieve the best possible performance.

5.9

Receiver

5.9.1

IF Frequency

The IF frequency is derived from the crystal frequency as shown in Equation 12.

(12)

Where:

ADC_DIV[2:0] is set in the MODEM register.

The analog filter succeeding the mixer is used for wideband and anti-alias filtering, which is important for

the blocking performance at 1 MHz and larger offsets. This filter is fixed and centered on the nominal IF

frequency of 307.2 kHz. The bandwidth of the analog filter is about 160 kHz.

Using crystal frequencies which gives an IF frequency within 300 to 320 kHz means that the analog filter

can be used (assuming low frequency deviations and low data rates).

Large offsets, however, from the nominal IF frequency will give an un-symmetric filtering (variation in

group delay and different attenuation) of the signal, resulting in decreased sensitivity and selectivity. See

AN022 CC1020 Crystal Frequency Selection (SWRA070) for more details.

For IF frequencies other than 300 to 320 kHz and for high frequency deviation and high data rates

(typically

≥ 76.8 kBaud) the analog filter must be bypassed by setting FILTER_BYPASS = 1 in the FILTER

The IF frequency is always the ADC clock frequency divided by 4. The ADC clock frequency should

therefore be as close to 1.2288 MHz as possible.

5.9.2

Receiver Channel Filter Bandwidth

In order to meet different channel spacing requirements, the receiver channel filter bandwidth is

programmable. It can be programmed from 9.6 to 307.2 kHz.

The minimum receiver channel filter bandwidth depends on baud rate, frequency separation and crystal

tolerance.

The signal bandwidth must be smaller than the available receiver channel filter bandwidth. The signal

bandwidth (SBW) can be approximated by (Carson’s rule) shown in Equation 13.

SBW = 2 × fm + 2 × frequency deviation

(13)

Where:

fm is the modulating signal.

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC1020

CC1020-RTR1 Datenblatt(PDF) 27 Page - Texas Instruments

CC1020-RTR1 Datenblatt(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

Datenblatt Download

Link URL