CC1020-RTR1 datasheet(5/95 Pages) TI1

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PCLK 1

AVDD

RF_OUT

AVDD

RF_IN

AVDD

R_BIAS

DIO 8

DCLK 7

DGND 6

DVDD 5

DGND 4

PDO 3

PDI 2

32 31 30 29 28 27 26 25

AGND

Exposed die

attached pad

CC1020

www.ti.com

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

Terminal Configuration and Functions

3.1

Pin Diagram

Figure 3-1 shows pin names and locations for the CC1020 device.

The CC1020 comes in a QFN 32-type package.

Figure 3-1. Package 7-mm × 7-mm VQFNP (Top View)

3.2

Pin Configuration

Table 3-1 provides an overview of the CC1020 pinout.

Table 3-1. Pin Attributes(1)(2)

PIN NO.

PIN NAME

TYPE

DESCRIPTION

Exposed die attached pad. Must be soldered to a solid ground plane as

—

AGND

Ground (analog)

this is the ground connection for all analog modules. See Section 6.3 for

more details.

PCLK

Digital input

Programming clock for SPI configuration interface

PDI

Digital input

Programming data input for SPI configuration interface

PDO

Digital output

Programming data output for SPI configuration interface

DGND

Ground (digital)

Ground connection (0 V) for digital modules and digital I/O

DVDD

Power (digital)

Power supply (3 V typical) for digital modules and digital I/O

DGND

Ground (digital)

Ground connection (0 V) for digital modules (substrate)

Clock for data in both receive and transmit mode.

DCLK

Digital output

Can be used as receive data output in asynchronous mode

Data input in transmit mode; data output in receive mode.

DIO

Digital input/output

Can also be used to start power-up sequencing in receive

PLL Lock indicator, active low. Output is asserted (low) when PLL is in

LOCK

Digital output

lock. The pin can also be used as a general digital output, or as receive

data output in synchronous NRZ/Manchester mode

XOSC_Q1

Analog input

Crystal oscillator or external clock input

XOSC_Q2

Analog output

Crystal oscillator

AVDD

Power (analog)

Power supply (3 V typical) for crystal oscillator

AVDD

Power (analog)

Power supply (3 V typical) for the IF VGA

General digital output. Can be used for controlling an external LNA if

LNA_EN

Digital output

higher sensitivity is needed.

(1)

DCLK, DIO and LOCK are high-impedance (3-state) in power down (BIAS_PD = 1 in the MAIN register).

(2)

The exposed die attached pad must be soldered to a solid ground plane as this is the main ground connection for the chip.

Terminal Configuration and Functions

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