CC1020-RTR1 datasheet(15/95 Pages) TI1

15 / 95 page

CC1020

www.ti.com

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

4.10 Digital Inputs and Outputs

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V,

fC = 14.7456 MHz if nothing else stated.

PARAMETER

MIN

TYP

MAX

UNIT

CONDITION

Logic "0" input voltage

0.3 × VDD

Logic "1" input voltage

0.7 × VDD

VDD

Output current –2.0 mA,

Logic "0" output voltage

0.4

3.0-V supply voltage

Output current 2.0 mA,

Logic "1" output voltage

2.5

VDD

3.0-V supply voltage

Input signal equals GND.

PSEL has an internal pullup

Logic “0” input current

N/A

–1

µA

resistor and during

configuration the current will

be –350 µA.

Logic “1” input current

N/A

µA

Input signal equals VDD

TX mode, minimum time DIO

must be ready before the

DIO setup time

positive edge of DCLK. Data

should be set up on the

negative edge of DCLK.

TX mode, minimum time DIO

must be held after the

DIO hold time

positive edge of DCLK. Data

should be set up on the

negative edge of DCLK.

Serial interface (PCLK, PDI, PDO and PSEL) timing

See Table 5-1 for more

specification

details

0 V on LNA_EN, PA_EN

0.90

pins

0.5 V on LNA_EN,

0.87

PA_EN pins

Source current

1.0 V on LNA_EN,

0.81

PA_EN pins

1.5 V on LNA_EN,

0.69

Pin drive,

PA_EN pins

See Figure 5-32 for more

LNA_EN,

details.

3.0 V on LNA_EN,

PA_EN

0.93

PA_EN pins

2.5 V on LNA_EN,

0.92

PA_EN pins

Sink current

2.0 V on LNA_EN,

0.89

PA_EN pins

1.5 V on LNA_EN,

0.79

PA_EN pins

Specifications

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