CC1020-RTR1 datasheet(34/95 Pages) TI1

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CC1020

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

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For high frequency deviation and high data rates (typically

≥ 76.8 kBaud) the analog filter succeeding the

mixer must be bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the image

rejection is degraded.

The image rejection is reduced for low supply voltages (typically < 2.5 V) when operating in the 402 to 470

MHz frequency range.

5.9.7

Blocking and Selectivity

Figure 5-13 shows the blocking/selectivity at 433 MHz, 12.5 kHz channel spacing. Figure 5-14 shows the

blocking/selectivity at 868 MHz, 25 kHz channel spacing. The blocking rejection is the ratio between a

modulated blocker (interferer) and a wanted signal 3 dB above the sensitivity limit.

Figure 5-13. Typical Blocker Rejection

Figure 5-14. Typical Blocker Rejection

Carrier Frequency Set to 434.3072 MHz

Carrier Frequency Set to 868.3072 MHz

(12.5 kHz Channel Spacing, 12.288 kHz Receiver Channel Filter

(25 kHz Channel Spacing, 19.2 kHz Receiver Channel Filter

Bandwidth)

5.9.8

Linear IF Chain and AGC Settings

CC1020 is based on a linear IF chain where the signal amplification is done in an analog VGA (Variable

Gain Amplifier). The gain is controlled by the digital part of the IF chain after the ADC (Analog to Digital

Converter). The AGC (Automatic Gain Control) loop ensures that the ADC operates inside its dynamic

range by using an analog/digital feedback loop.

The maximum VGA gain is programmed by the VGA_SETTING[4:0] in the VGA3 register. The VGA gain

is programmed in approximately 3 dB/LSB. The VGA gain should be set so that the amplified thermal

noise from the front-end balance the quantization noise from the ADC. Therefore the optimum maximum

VGA gain setting will depend on the channel filter bandwidth.

A digital RSSI is used to measure the signal strength after the ADC. The CS_LEVEL[4:0] in the VGA4

Further explanation can be found in Figure 5-15.

The VGA gain will be changed according to a threshold set by the VGA_DOWN[2:0] in the VGA3 register

and the VGA_UP[2:0] in the VGA4 register. Together, these two values specify the signal strength limits

used by the AGC to adjust the VGA gain.

To avoid unnecessary tripping of the VGA, an extra hysteresis and filtering of the RSSI samples can be

added. The AGC_HYSTERESIS bit in the VGA2 register enables this.

The time dynamics of the loop can be altered by the VGA_BLANKING bit in the ANALOG register, and

VGA_FREEZE[1:0] and VGA_WAIT[2:0] bits in the VGA1 register.

When VGA_BLANKING is activated, the VGA recovery time from DC offset spikes after a gain step is

reduced.

Detailed Description

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