WM8912 datasheet(75/129 Pages) CIRRUS

75 / 129 page

Production Data

WM8912

PD, Rev 4.1, February 2013

GPIO OUTPUTS FROM FLL

The WM8912 has an internal signal which indicates whether the FLL Lock has been achieved. The

FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event

- see “Interrupts”.

The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See

“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL

Lock signal.

The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the

FLL Clock may be output even if the FLL is not selected as the WM8912 SYSCLK source. The

clocking configuration is illustrated in Figure 44. See “General Purpose Input/Output (GPIO)” for

details of how to configure a GPIO pin to output the FLL Clock.

EXAMPLE FLL SETTINGS

Table 50 provides example FLL settings for generating common SYSCLK frequencies from a variety

of low and high frequency reference inputs.

FREF

FOUT

FLL_CLK_

REF_DIV

FVCO

FLL_N

FLL_K

FLL_

FRATIO

FLL_

OUTDIV

FLL_

FRACN

_ENA

32.768

kHz

12.288

MHz

Divide by 1

(0h)

98.304

MHz

187

(0BBh)

0.5

(8000h)

(4h)

(7h)

32.768

kHz

11.288576

MHz

Divide by 1

(0h)

90.308608

MHz

344

(158h)

0.5

(8000h)

(3h)

(7h)

32.768

kHz

11.2896

MHz

Divide by 1

(0h)

90.3168

MHz

344

(158h)

0.53125

(8800h)

(3h)

(7h)

kHz

12.288

MHz

Divide by 1

(0h)

98.304

MHz

256

(100h)

(0000h)

(3h)

(7h)

12.000

MHz

12.288

MHz

Divide by 1

(0h)

98.3040

MHz

(008h)

0.192

(3127h)

(0h)

(7h)

12.000

MHz

11.289597

MHz

Divide by 1

(0h)

90.3168

MHz

(007h)

0.526398

(86C2h)

(0h)

(7h)

12.288

MHz

12.288

MHz

Divide by 1

(0h)

98.304

MHz

(008h)

(0000h)

(0h)

(7h)

12.288

MHz

11.2896

MHz

Divide by 1

(0h)

90.3168

MHz

(007h)

0.35

(599Ah)

(0h)

(7h)

13.000

MHz

12.287990

MHz

Divide by 1

(0h)

98.3040

MHz

(007h)

0.56184

(8FD5h)

(0h)

(7h)

13.000

MHz

11.289606

MHz

Divide by 1

(0h)

90.3168

MHz

(006h)

0.94745

(F28Ch)

(0h)

(7h)

19.200

MHz

12.287988

MHz

Divide by 2

(1h)

98.3039

MHz

(005h)

0.119995

(1EB8h)

(0h)

(7h)

19.200

MHz

11.289588

MHz

Divide by 2

(1h)

90.3168

MHz

(004h)

0.703995

(B439h)

(0h)

(7h)

Table 50 Example FLL Settings

WM8912 Datenblatt(PDF) 75 Page - Cirrus Logic

WM8912 Datenblatt(HTML) 75 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL