WM8912 datasheet(99/129 Pages) CIRRUS

99 / 129 page

Production Data

WM8912

PD, Rev 4.1, February 2013

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R22 (16h)

Clock Rates

MCLK_INV

MCLK Invert

0 = MCLK not inverted

1 = MCLK inverted

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = FLL output

TOCLK_RATE

TOCLK Rate Divider (/2)

0 = f / 2

1 = f / 1

OPCLK_ENA

GPIO Clock Output Enable

0 = disabled

1 = enabled

CLK_SYS_EN

System Clock enable

0 = Disabled

1 = Enabled

CLK_DSP_EN

DSP Clock enable

0 = Disabled

1 = Enabled

TOCLK_ENA

Zero Cross timeout enable

0 = Disabled

1 = Enabled

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R24 (18h)

Audio

Interface 0

DACL_DATINV

Left DAC Invert

0 = Left DAC output not inverted

1 = Left DAC output inverted

DACR_DATIN

Right DAC Invert

0 = Right DAC output not inverted

1 = Right DAC output inverted

10:9

DAC_BOOST

[1:0]

DAC Digital Input Volume Boost

00 = 0dB

01 = +6dB (Input data must not exceed -6dBFS)

10 = +12dB (Input data must not exceed -12dBFS)

11 = +18dB (Input data must not exceed -18dBFS)

AIFDACL_SRC

Left DAC Data Source Select

0 = Left DAC outputs left channel data

1 = Left DAC outputs right channel data

AIFDACR_SR

Right DAC Data Source Select

0 = Right DAC outputs left channel data

1 = Right DAC outputs right channel data

DAC_COMP

DAC Companding Enable

0 = disabled

1 = enabled

DAC_COMPM

ODE

DAC Companding Type

0 = µ-law

1 = A-law

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