5CSXFC6D6F31C7N datasheet(67/93 Pages) INTEL

67 / 93 page

CAN Interface

The maximum controller area network (CAN) data rate is 1 Mbps.

HPS JTAG Timing Specifications

Table 54.

HPS JTAG Timing Parameters and Values for Cyclone V Devices

Symbol

Description

Min

Max

Unit

tJCP

TCK clock period

—

tJCH

TCK clock high time

—

tJCL

TCK clock low time

—

tJPSU (TDI)

TDI JTAG port setup time

—

tJPSU (TMS)

TMS JTAG port setup time

—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock to output

—

12(73)

tJPZX

JTAG port high impedance to valid output

—

14(73)

tJPXZ

JTAG port valid output to high impedance

—

14(73)

Configuration Specifications

This section provides configuration specifications and timing for Cyclone V devices.

(73) A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank

= 2.5 V, or 14 ns if it equals 1.8 V.

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

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Cyclone V Device Datasheet

5CSXFC6D6F31C7N Datenblatt(PDF) 67 Page - Intel Corporation

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