5CSXFC6D6F31C7N datasheet(72/93 Pages) INTEL

72 / 93 page

Symbol

Parameter

Minimum

Maximum

Unit

tCF2CK(83)

nCONFIG

high to first rising edge on DCLK

1506

—

µs

tST2CK(83)

nSTATUS

high to first rising edge of DCLK

—

µs

tDSU

DATA[]

setup time before rising edge on DCLK

5.5

—

tDH

DATA[]

hold time after rising edge on DCLK

N – 1/fDCLK(84)

—

tCH

DCLK

high time

0.45 × 1/fMAX

—

tCL

DCLK

low time

0.45 × 1/fMAX

—

tCLK

DCLK

period

1/fMAX

—

fMAX

DCLK

frequency (FPP ×8/ ×16)

—

125

MHz

Input rise time

—

Input fall time

—

tCD2UM

CONF_DONE

high to user mode(85)

175

437

µs

tCD2CU

CONF_DONE

high to CLKUSR enabled

4 × maximum DCLK period

—

tCD2UMC

CONF_DONE

high to user mode with CLKUSR option on

tCD2CU + (Tinit × CLKUSR period)

—

Tinit

Number of clock cycles required for device initialization

8,576

—

Cycles

Related Information

FPP Configuration Timing

Provides the FPP configuration timing waveforms.

(82) This value can be obtained if you do not delay configuration by externally holding nSTATUS low.

(83) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.

(84) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system.

(85) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

Cyclone V Device Datasheet

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