5CSXFC6D6F31C7N datasheet(74/93 Pages) INTEL

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•

AS Configuration Timing

Provides the AS configuration timing waveform.

•

Evaluating Data Setup and Hold Timing Slack chapter, AN822: Intel FPGA Configuration Device Migration Guideline

DCLK Frequency Specification in the AS Configuration Scheme

Table 61.

DCLK Frequency Specification in the AS Configuration Scheme

This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal

oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.

Parameter

Minimum

Typical

Maximum

Unit

DCLK

frequency in AS configuration scheme

5.3

7.9

12.5

MHz

10.6

15.7

25.0

MHz

21.3

31.4

50.0

MHz

42.6

62.9

100.0

MHz

Passive Serial (PS) Configuration Timing

Table 62.

PS Timing Parameters for Cyclone V Devices

Symbol

Parameter

Minimum

Maximum

Unit

tCF2CD

nCONFIG

low to CONF_DONE low

—

600

tCF2ST0

nCONFIG

low to nSTATUS low

—

600

tCFG

nCONFIG

low pulse width

—

µs

tSTATUS

nSTATUS

low pulse width

268

1506(90)

µs

tCF2ST1

nCONFIG

high to nSTATUS high

—

1506(91)

µs

tCF2CK(92)

nCONFIG

high to first rising edge on DCLK

1506

—

µs

continued...

(90) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

(91) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

Cyclone V Device Datasheet

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