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5CSXFC6D6F31C7N Datenblatt(PDF) 78 Page - Intel Corporation |
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5CSXFC6D6F31C7N Datenblatt(HTML) 78 Page - Intel Corporation |
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78 / 93 page ![]() Minimum Configuration Time Estimation Table 65. Minimum Configuration Time Estimation for Cyclone V Devices The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Cyclone V Devices table. Variant Member Code Active Serial(97) Fast Passive Parallel(98) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) Cyclone V E A2 4 100 53 16 125 11 A4 4 100 53 16 125 11 A5 4 100 85 16 125 17 A7 4 100 140 16 125 28 A9 4 100 257 16 125 51 Cyclone V GX C3 4 100 36 16 125 7 C4 4 100 85 16 125 17 C5 4 100 85 16 125 17 C7 4 100 140 16 125 28 C9 4 100 257 16 125 51 Cyclone V GT D5 4 100 85 16 125 17 D7 4 100 140 16 125 28 D9 4 100 257 16 125 51 Cyclone V SE A2 4 100 85 16 125 17 A4 4 100 85 16 125 17 A5 4 100 140 16 125 28 A6 4 100 140 16 125 28 continued... (97) DCLK frequency of 100 MHz using external CLKUSR. (98) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Cyclone V Device Datasheet CV-51002 | 2019.01.25 Cyclone V Device Datasheet Send Feedback 78 |
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