5CSXFC6D6F31C7N datasheet(43/93 Pages) INTEL

43 / 93 page

Symbol

Parameter

Condition

Min

Typ

Max

Unit

tFOUTPJ_IO(58)(60)(61)

Period jitter for clock output on a regular I/O

in fractional PLL

FOUT ≥ 100 MHz

—

650

ps (p-p)

FOUT < 100 MHz

—

mUI (p-p)

tOUTCCJ_IO(58)(60)

Cycle-to-cycle jitter for clock output on

regular I/O in integer PLL

FOUT ≥ 100 MHz

—

650

ps (p-p)

FOUT < 100 MHz

—

mUI (p-p)

tFOUTCCJ_IO(58)(60)(61)

Cycle-to-cycle jitter for clock output on

regular I/O in fractional PLL

FOUT ≥ 100 MHz

—

650

ps (p-p)

FOUT < 100 MHz

—

mUI (p-p)

tCASC_OUTPJ_DC(58)(62)

Period jitter for dedicated clock output in

cascaded PLLs

FOUT ≥ 100 MHz

—

300

ps (p-p)

FOUT < 100 MHz

—

mUI (p-p)

tDRIFT

Frequency drift after PFDENA is disabled for a

duration of 100 µs

—

±10

dKBIT

Bit number of Delta Sigma Modulator (DSM)

—

Bits

kVALUE

Numerator of fraction

—

128

8388608

2147483648

—

fRES

Resolution of VCO frequency

fINPFD = 100 MHz

390625

5.96

0.023

Related Information

Memory Output Clock Jitter Specifications on page 49

Provides more information about the external memory interface clock output jitter specifications.

(61) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.

(62) The cascaded PLL specification is only applicable with the following conditions:

• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz

• Downstream PLL: Downstream PLL BW > 2 MHz

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

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Cyclone V Device Datasheet

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