5CSXFC6D6F31C7N datasheet(69/93 Pages) INTEL

69 / 93 page

Symbol

Description

Min

Max

Unit

tJPCO

JTAG port clock to output

—

11(76)

tJPZX

JTAG port high impedance to valid output

—

14(76)

tJPXZ

JTAG port valid output to high impedance

—

14(76)

FPP Configuration Timing

DCLK-to-DATA[] Ratio (r) for FPP Configuration

Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the

compression feature.

Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per

second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the

DATA[]

rate in Wps.

Cyclone V devices use additional clock cycles to decrypt and decompress the configuration data. If the DCLK-to-DATA[] ratio

is greater than 1, at the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the

last data is latched into the Cyclone V device.

Table 57.

DCLK-to-DATA[] Ratio for Cyclone V Devices

Configuration Scheme

Encryption

Compression

DCLK-to-DATA[] Ratio (r)

FPP (8-bit wide)

Off

FPP (16-bit wide)

Off

continued...

(76) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank =

2.5 V, or 14 ns if it equals 1.8 V.

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

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Cyclone V Device Datasheet

5CSXFC6D6F31C7N Datenblatt(PDF) 69 Page - Intel Corporation

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