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ADP5310AREZN-R7 Datenblatt(PDF) 4 Page - Analog Devices |
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ADP5310AREZN-R7 Datenblatt(HTML) 4 Page - Analog Devices |
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4 / 28 page ![]() ADP5310 Data Sheet Rev. A | Page 4 of 28 SPECIFICATIONS VIN = 6 V, VREG = 3.9 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments INPUT SUPPLY VOLTAGE RANGE VIN 2.7 15.0 V PVIN1 and PVIN2 pins QUIESCENT CURRENT PVIN1 and PVIN2 pins Operating Quiescent Current Standby Operation IQ1 700 1850 nA −40°C ≤ TJ ≤ +85°C, EN1 = SYNC/MODE = low 700 3800 nA −40°C ≤ TJ ≤ +125°C, EN1 = SYNC/MODE = low PWM Operation IQ3 1.4 1.65 mA EN1 = SYNC/MODE = high UNDERVOLTAGE LOCKOUT UVLO PVIN2 pin UVLO Threshold Rising VUVLO_RISING 2.55 2.75 V Falling VUVLO_FALLING 2.15 2.40 V Hysteresis VHYS 150 mV OSCILLATOR CIRCUIT For Channel 1 and Channel 2, PWM mode Switching Frequency fSW 1050 1200 1350 kHz 525 600 675 kHz Feedback (FB) Threshold of Frequency Fold VOSC_FOLD 0.3 V SYNCHRONIZATION THRESHOLD SYNC Clock Range SYNCCLOCK 400 800 kHz fSW = 600 kHz SYNCCLOCK 800 1400 kHz fSW = 1.2 MHz SYNC High Level Threshold SYNCHIGH 1.2 V SYNC Low Level Threshold SYNCLOW 0.4 V SYNC Pulse On Time Range SYNCON 80 1/fSW − 150 ns EN1 and EN3 Input High Level Threshold VIH 1.2 V Input Low Level Threshold VIL 0.4 V Input Leakage Current ILEAKAGE 300 nA INTERNAL POWER GOOD Internal Power-Good Threshold VPWRGD(RISE) 88 92 96 % Internal Power-Good Hysteresis VPWRGD(HYS) 5 % Internal Power-Good Rising Delay tPWRGD_RISE 16 Clock cycles Internal Power-Good Falling Delay tPWRGD_FALL 1 µs Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 10 40 nA Output Low Voltage for PWRGD Pin VPWRGD_LOW 50 100 mV IPWRGD = 100 µA INTERNAL REGULATOR VREG Output Voltage VREG 3.6 3.9 4.2 V THERMAL SHUTDOWN Threshold TSHDN 135 °C Hysteresis THYS 15 °C |
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