ADP5310AREZN-R7 datasheet(22/28 Pages) AD

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ADP5310

Data Sheet

Rev. A | Page 22 of 28

ADJUSTABLE OUTPUT VOLTAGE PROGRAMMING

The ADP5310 features an adjustable output voltage range from

0.8 V to 5.0 V. The output voltage is set by the ratio of two external

resistors. The device servos the output to maintain the voltage at

the FBx pin at 0.8 V, referenced to ground; the current in R1 is

then equal to 0.8 V/R2 plus the FB pin bias current. The bias

current of the FBx pin, 15 nA at 25°C, flows through R2 into the

FBx pin.

The output voltage is calculated using the equation

VOUT = 0.8 V(1 + R1/R2) + (IFB_ADJ)(R1)

To minimize errors in the output voltage caused by the bias

current of the FBx pin, maintain a value of R2 that is less than

200 kΩ. For example, when R1 and R2 each equal 200 kΩ, the

output voltage is 1.6 V. The output voltage error introduced by

the FBx pin bias current is 3 mV, or 0.187%, assuming a typical

FBx pin bias current of 15 nA at 25°C.

Note that in shutdown mode, the output is turned off and the

divider current is zero.

EFFICIENCY

Efficiency is the ratio of output power to input power. The high

efficiency of the ADP5310 has two distinct advantages. First,

only a small amount of power is lost in the dc-to-dc converter

package, which in turn, reduces thermal constraints. Second,

the high efficiency delivers the maximum output power for the

given input power, thereby extending battery life in portable

applications.

Power Switch Conduction Losses

Power switch dc conduction losses are caused by the flow of

output current through the P-channel power switch and the

N-channel synchronous rectifier, which have internal resis-

tances (RDS(ON)) associated with them. The amount of power

loss is approximated by

PSW_COND = (RDS(ON)_P × D + RDS(ON)_N × (1 − D)) × IOUT2

where:

OUT

D =

The internal resistance of the power switches increases with tem-

perature and increases when the input voltage is less than 5.5 V.

Inductor Losses

Inductor conduction losses are caused by the flow of current

through the inductor, which has an internal DCR associated

with it. Larger size inductors have smaller DCR, which can

decrease inductor conduction losses. Inductor core losses relate

to the magnetic permeability of the core material. Because the

ADP5310 has high switching frequency dc-to-dc regulators,

shielded ferrite core material is recommended because of its low

EMI.

To estimate the total amount of power lost in the inductor (PL),

use the following equation:

PL = DCR × IOUT2 + Core Losses

Driver Losses

Driver losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. Each time a power device gate is turned on and turned

off, the driver transfers a charge from the input supply to the

gate, and then from the gate to ground.

Estimate driver losses using the following equation:

PDRIVER = (CGATE_P + CGATE_N) × VIN2 × fSW

where:

CGATE_P is the gate capacitance of the internal high-side switch.

CGATE_N is the gate capacitance of the internal low-side switch.

fSW is the switching frequency.

The typical value for both gate capacitances, CGATE_P and CGATE_N,

is 150 pF.

Transition Losses

Transition losses occur because the P-channel switch cannot

turn on or turn off instantaneously. In the middle of an SWx

node transition, the power switch provides all of the inductor

current. The source-to-drain voltage of the power switch is half

of the input voltage, resulting in power loss. Transition losses

increase with both load current and input voltage and occur

twice for each switching cycle.

Use the following equation to estimate transition losses:

PTRAN = VIN/2 × IOUT × (tR + tF) × fSW

where:

tR is the rise time of the SWx node.

tF is the fall time of the SWx node.

The typical value for the rise and fall times, tR and tF, is 2 ns.

RECOMMENDED BUCK EXTERNAL COMPONENTS

The recommended external components for use with the

ADP5310 are listed in Table 6, Table 7, and Table 8.

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