ADP5310AREZN-R7 datasheet(18/28 Pages) AD

18 / 28 page

ADP5310

Data Sheet

Rev. A | Page 18 of 28

THEORY OF OPERATION

The ADP5310 is an ultralow power management unit that

combines dual buck regulators and one load switch in a 16-lead

TSSOP_EP package to meet demanding performance and board

space requirements. The device enables direct connection to the

wide input voltage range of 2.7 V to 15 V, allowing the use of

multiple alkaline/NiMH or lithium cells and other power sources.

BUCK REGULATOR OPERATION MODES

PWM Mode

In PWM mode, the buck regulators in the ADP5310 operate at a

fixed frequency that is set by an internal oscillator. At the start

of each oscillator cycle, the high-side MOSFET switch turns on and

sends a positive voltage across the inductor. The inductor current

increases until the current sense signal exceeds the peak current

threshold of the inductor that turns off the high-side MOSFET

switch and turns on the low-side MOSFET. This places a negative

voltage across the inductor, causing the inductor current to reduce.

The low-side MOSFET stays on for the remainder of the cycle.

PSM Mode

The ADP5310 smoothly transitions to the variable frequency

PSM mode of operation when the load current decreases below

the pulse skipping threshold current, IMIN. For the peak current

of the inductor based on the input and output voltages, the design

of the IMIN value is based on the recommended inductor values.

Deviating from the recommended inductor value for a particular

output voltage results in shifting the PSM to PWM threshold

and may result in the device entering discontinuous mode (DCM).

As long as the required peak inductor current is above IMIN, the

regulator remains in PWM mode. As the load decreases, the PSM

circuitry prevents the peak inductor current from dropping below

the PSM peak current value. This circuitry causes the regulator

to supply more current to the output than the load requires,

resulting in the output voltage increasing and the output of the

internal compensation node of the error amplifier, VCOMP,

decreasing.

When the FB1 pin voltage rises above 1% of the nominal output

voltage and the VCOMP node voltage is below a predetermined

PSM threshold voltage level, the regulator enters skip mode.

While in skip mode, the high-side and low-side switches and a

majority of the circuitry are disabled to allow a low skip mode

quiescent current as well as high efficiency performance.

During skip mode, the output voltage decreases as the output

capacitor discharges into the load. Fixed frequency operation starts

when the FB1 voltage reaches the nominal output voltage. When

the load requirement increases past the IMIN peak current level,

the VCOMP node rises and the PWM control loop sets the duty

cycle. While the device is entering and exiting skip mode, the

PSM voltage ripple is larger than 1% because of the delay in the

comparators.

Hysteresis Mode

In hysteresis mode, the buck regulator in the ADP5310 charges

the output voltage slightly higher than its nominal output

voltage with PWM pulses by regulating the constant peak

inductor current. When the output voltage increases until the

output sense signal exceeds the hysteresis upper threshold, the

regulator enters standby mode. In standby mode, the high-side

and low-side MOSFET and a majority of the circuitry are

disabled to allow a low quiescent current as well as high

efficiency performance.

During standby mode, the output capacitor supplies the energy

into the load and the output voltage decreases until it falls below

the hysteresis comparator lower threshold. The buck regulator

wakes up and generates the PWM pulses to charge the output

again.

Because the output voltage occasionally enters standby mode

and then recovers, the output voltage ripple in hysteresis mode

is larger than the ripple in PWM mode.

Mode Selection

The buck regulator in Channel 1 uses the default automatic

PSM/PWM mode for excellent light load efficiency. Current

mode, constant frequency PWM mode can be programmed by

the factory fuse for excellent stability and transient performance.

The buck regulator in Channel 2 includes the SYNC/MODE pin,

allowing configuration in hysteresis mode or PWM mode.

When a logic high level is applied to the SYNC/MODE pin, the

buck regulator in Channel 2 is forced to operate in PWM mode.

In PWM mode, the regulator can supply up to 300 mA of output

current. The regulator can provide lower output ripple and

lower 1/f output noise in PWM mode, which benefits noise

sensitive applications.

When a logic low level is applied to the SYNC/MODE pin, the

buck regulator in Channel 2 is forced to operate in hysteresis

mode. In hysteresis mode, the regulator draws only 700 nA of

quiescent current to regulate the output under zero load, which

allows Channel 2 to act as a keep-alive power supply in a

battery-powered system. In hysteresis mode, the regulator

supplies up to 50 mA of output current with a relatively large

output ripple compared to PWM mode.

The user can alternate between hysteresis mode and PWM

mode during operation. The flexible configuration capability

during operation of the device enables efficient power

management to meet high efficiency and low output ripple

requirements when the system switches between active mode

and standby mode.

ADP5310AREZN-R7 Datenblatt(PDF) 18 Page - Analog Devices

ADP5310AREZN-R7 Datenblatt(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datenblatt Download

Link URL