ADP5310

Data Sheet

Rev. A | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PVIN2

NC

SW2

VOUT3

FB2

PGND2

PVIN1

PGND1

EN1

FB1

VREG

EN3

AGND

SYNC/MODE

PWRGD

SW1

ADP5310

TOP VIEW

(Not to Scale)

NOTES

2. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL

COPPER GROUND PLANE UNDERNEATH THE IC FOR

THERMAL DISSIPATION.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

PVIN1

Power Input of Channel 1. This pin must be connected to PVIN2.

2

PVIN2

Power Input of Channel 2 and Internal Linear Regulator.

3

NC

No Connect. This pin is not internally connected. Leave this pin floating.

4

SW2

Switching Node Output of Channel 2.

5

PGND2

Power Ground of Channel 2.

6

FB2

Feedback Sensing Input of Channel 2.

7

VOUT3

Power Output of Channel 3.

8

EN3

Enable Input of Channel 3.

9

AGND

Analog Ground.

10

VREG

Output of the Internal Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground.

11

SYNC/MODE

Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock,

connect this pin to an external clock with a frequency from 400 kHz to 1.4 MHz.

PWM or Hysteresis Mode Selection Pin of Channel 2 (MODE). When this pin is logic high, the regulator operates

in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode.

12

PWRGD

Power-Good Signal Output. This open-drain output is the power-good signal of Channel 1.

13

FB1

Feedback Sensing Input of Channel 1.

14

EN1

Enable Input of Channel 1.

15

PGND1

Power Ground of Channel 1.

16

SW1

Switching Node Output of Channel 1.

EPAD

Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal

dissipation.