ADP5310AREZN-R7 datasheet(19/28 Pages) AD

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Data Sheet

ADP5310

Rev. A | Page 19 of 28

ADJUSTABLE AND FIXED OUTPUT VOLTAGES

The buck regulator in Channel 1 provides adjustable and fixed

output voltage settings via the factory fuse. For the adjustable

output settings, use an external resistor divider to set the

desired output voltage via the feedback reference voltage (0.8 V

for Channel 1).

The buck regulator in Channel 2 provides adjustable and fixed

output voltage settings via the factory fuse as well. Because the

input source of the load switch in Channel 3 shares the FB2 pin,

the load switch in Channel 3 is unusable when Channel 2 is

configured in adjustable output mode via the factory fuse.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry monitors the input voltage level of the

ADP5310 in the PVIN2 pin. When the input voltage falls below

2.40 V (typical), all channels turn off. After the input voltage

rises above 2.55 V (typical), the soft start period is initiated, and

the corresponding channel is enabled when the ENx pin is high.

ENABLE AND SHUTDOWN FEATURES

The ADP5310 uses the enable pins (EN1 and EN3) at logic

levels to enable and disable Channel 1 and Channel 3. The

associated channel begins operation with soft start when the

enable pin is toggled from logic low to logic high. Pulling an

enable pin low forces the associated channel into a shutdown

condition.

The buck regulator in Channel 2 is always alive as long as the

PVIN2 voltage is above the UVLO threshold.

INTERNAL LINEAR REGULATOR (VREG)

The internal linear VREG regulator in the ADP5310 provides a

stable 3.9 V power supply for the bias voltage of the MOSFET

drivers and internal control circuits. Connect a 1.0 µF ceramic

capacitor between VREG and ground.

OSCILLATOR AND SYNCHRONIZATION

The ADP5310 ensures that both buck regulators operate at the

same switching frequency when both buck regulators are in

PWM mode.

The ADP5310 offers 600 kHz or 1.2 MHz switching frequency

options in PWM operation mode via the factory fuse. The

default switching frequency is 1.2 MHz.

The switching frequency of theADP5310 can be synchronized to

an external clock with a frequency range from 400 kHz to 1.4 MHz.

The ADP5310 automatically detects the presence of an external

clock applied to the SYNC/MODE pin, and the switching

frequency transitions to the frequency of the external clock.

When the external clock signal stops, the device automatically

switches back to the internal clock and continues to operate.

CURRENT LIMIT

The buck regulators in the ADP5310 have protection circuitry

that limit the direction and the amount of current to a certain

level that flows through the high-side MOSFET and the low-

side MOSFET in cycle-by-cycle mode. The positive current

limit on the high-side MOSFET limits the amount of current

that can flow from the input to the output. The negative current

limit on the low-side MOSFET prevents the inductor current

from reversing direction and flowing out of the load.

SHORT-CIRCUIT PROTECTION

The buck regulators in theADP5310 include frequency foldback to

prevent current runaway on a hard short. When the output voltage

at the feedback pin falls below 0.3 V, indicating the possibility of

a hard short at the output, the switching frequency (in PWM

mode) is reduced to ¼ of the internal oscillator frequency. The

reduction in the switching frequency allows more time for the

inductor to discharge, preventing a runaway of output current.

SOFT START

The ADP5310 has an internal soft start function that ramps up

the output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This prevents possible input voltage

drops when a battery or a high impedance power source is

connected to the input of the device. The default soft start time

is 350 µs for the regulators in Channel 1 and Channel 2.

Different soft start times can be programmed for each channel

by the factory fuse.

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5310 include a precharged

start-up feature to protect the low-side FETs from damage

during startup. If the output voltage is precharged before the

regulator is turned on, the regulator prevents reverse inductor

current, which discharges the output capacitor until the internal

soft start reference voltage exceeds the precharged voltage on

the feedback pin.

100% DUTY OPERATION

With a drop in input voltage or with an increase in load current,

the buck regulator in the ADP5310 may reach a limit where,

even with the high-side MOSFET on 100% of the time, the

ADP5310 works in 100% duty operation and the output is lower

than the preset value.At this limit, the buck regulator transitions to

a mode where the high-side MOSFET switch stays on 100% of

the time. When the input conditions charge again and the

required duty cycle falls, the buck immediately restarts PWM

regulation without allowing overshoot on the output voltage.

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