Bit b7:b4

Don’t care bits - Read as '0'. (b7, b6, b5, b4) = (0, 0, 0, 0)

Bit b3:b1

C2, C1, C0: Configurable device address bits

b3, b2, b1 are used to configure up to eight possibilities of chip enable address:

•

(b3, b2, b1) = (0, 0, 0): the chip enable address is 000 (factory delivery value)

•

(b3, b2, b1) = (0, 0, 1): the chip enable address is 001

•

(b3, b2, b1) = (0, 1, 0): the chip enable address is 010

•

(b3, b2, b1) = (0, 1, 1): the chip enable address is 011

•

(b3, b2, b1) = (1, 0, 0): the chip enable address is 100

•

(b3, b2, b1) = (1, 0, 1): the chip enable address is 101

•

(b3, b2, b1) = (1, 1, 0): the chip enable address is 110

•

(b3, b2, b1) = (1, 1, 1): the chip enable address is 111

Bit b0

DAL: Device address lock bit

b0 locks the CDA register in read-only mode:

•

b0 = 0: bits b3, b2, b1, b0 can be modified

•

b0 = 1: bits b3, b2, b1, b0 cannot be modified and therefore the CDA register is frozen

Note:

bits b3 to b0 can be updated (if b0 = 0) in the same write instruction. Setting b0 from 0 to 1 is an

irreversible action.

C2, C1 and C0 and DAL define the chip enable address in the device select code and device address lock. These

bits can be written and re-configured with a write command.

At power up or after reprogramming, the device loads the last configuration of C2, C1, C0 and DAL values.

In order to prevent unwanted change of configurable device address bits, the M24256X proposes to protect the

CDA register, freezing permanently it in read-only mode. The update of the CDA register is disabled (read-only)

when the DAL bit is set to '1' (DAL = 1b).

In the same way, the update of the CDA register is enabled when the DAL bit is set to '0' (DAL = 0b).

Note:

Updating the DAL bit from 0 to 1 is an irreversible action: the C2, C1, C0 and DAL bits cannot be updated any

more.

4.3

Software write protection register (SWP)

As the M24256X-F is delivered in 4-ball WLCSP without write control (WC) input, the device provides a non-

volatile 8-bit register allowing the user to protect a specific area of the memory against the write instructions. The

SWP offers four non volatile bits to configure by the user:

•

Two bits to set the size of the write-protected memory and identified as block protect bits (BPn) bits

•

One bit to enable / disable the write protection of the desired area and identified as write protect activation

(WPA) bit

•

One bit to definitively freeze in read-only mode the SWP register and identified as write protection lock

(WPL) bit

This register can be written and read by issuing the read or write configurable device address instruction. These

instructions use the same protocol and format as the random address read or page write (from/into memory array)

except for the following differences (refer to Table 5, Table 6 and Table 7):

•

Device type identifier = 1010b

•

MSB address bits A15/A14/A13 must be equal to '101' (A15 = 1; A14 = 0; A13 = 1)

•

MSB address bits A12/A8 are don't care

•

LSB address bits A7/A0 are don't care

To prevent unwanted change of software write protection register bits, the M24256X-F proposes to protect the

SWP register, freezing it permanently in read-only mode. The update of the SWP register is disabled (read only)

when the WPL bit is set to '1' (WPL = 1b). In the same way, the update of the SWP register is enabled when the

WPL bit is set to '0' (WPL = 0b).

Updating the SWP bit from '0' to '1' is an irreversible action: the WPA, BP1, BP0 and WPL bits cannot be updated

any more.

When SWP is set to '1' and in case of write software write protection register, the device select and address bytes

are acknowledged, data byte is not acknowledged and write cycle does not start.

M24256X-F

Software write protection register (SWP)

DS12380 - Rev 2

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