M24256X-F datasheet(24/42 Pages) STMICROELECTRONICS

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6.8

Read operations on software write protection register

Following a start condition the bus master sends a device select code with the R/W bit (RW) set to 0. The device

acknowledges this and waits for the address bytes where the SWP register is located. The device responds to

each address byte with an acknowledge bit. Then, the bus master sends another start condition, and repeats the

device select code,with the RW bit set to 1. The device acknowledges this, and outputs the contents of the SWP

protection register.

To terminate the stream of data byte, the bus master must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 14.

After the successful completion of a read operation on SWP, the device internal address counter is not

incremented by one, to point to the next byte address. Reading more than one byte loops on reading the SWP

The SWP register cannot be read while a write cycle (tw) is ongoing.

Figure 14. Random read sequence on SWP register

Dev sel*

Byte addr

Data out

ACK

NO ACK

ACK

Dev sel*

* The seven most significant bits of the first device select code of a random read must be identical to the seven

most significant bits of the second device select code

M24256X-F

Read operations on software write protection register

DS12380 - Rev 2

page 24/42

M24256X-F Datenblatt(PDF) 24 Page - STMicroelectronics