2

Signal description

2.1

Serial clock (SCL)

SCL is an input. The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output

the data on SDA(out).

2.2

Serial data (SDA)

SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that

may be wire-AND with other open drain or open collector signals on the bus. A pull-up resistor must be connected

from serial data (SDA) to VCC (Figure 16 and Figure 17 indicate how to calculate the value of the pull-up resistor).

2.3

VSS (ground)

VSS is the reference for the VCC supply voltage.

2.4

Supply voltage (VCC)

2.4.1

Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified

[VCC(min), VCC(max)] range must be applied (see Table 9). In order to secure a stable DC supply voltage, it is

recommended to decouple the VCC line with a suitable capacitor (from 10 to 100 nF) close to the VCC / VSS

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write

instruction, until the completion of the internal write cycle (tW).

2.4.2

Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Table 9 in

Section 9 DC and AC parameters).

Once the VCC is greater than, or equal to, the minimum VCC level, the master must wait for at least TWU before

sending the first command to the device. See Table 15 and Table 16 for the value of the wake-up time parameter.

2.4.3

Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold

voltage. This threshold is lower than the minimum VCC operating voltage (see Table 9 in Section 9 DC and AC

parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode;

however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified

[VCC(min), VCC(max)] range (see Table 9 in Section 9 DC and AC parameters).

In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC

drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding

to any instruction sent to it.

2.4.4

Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached

after decoding a stop condition, assuming that there is no internal write cycle in progress).

M24256X-F

Signal description

DS12380 - Rev 2

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