Table 15. AC characteristics in Fast-mode

Symbol

Alt.

Parameter

Min.

Max.

Unit

fC

fSCL

Clock frequency

-

400

kHz

tCHCL

tHIGH

Clock pulse width high

600

-

ns

tCLCH

tLOW

Clock pulse width low

1300

-

ns

tQL1QL2(1)

tF

SDA (out) fall time

20

300

ns

tXH1XH2

tR

Input signal rise time

(2)

(2)

ns

tXL1XL2

tF

Input signal fall time

(2)

(2)

ns

tDXCH

tSU:DAT Data in set up time

100

-

ns

tCLDX

tHD:DAT Data in hold time

0

-

ns

tCLQX (3)

tDH

Data out hold time

100

-

ns

tCLQV (4)

tAA

Clock low to next data valid (access time)

-

900

ns

tCHDL

tSU:STA

Start condition setup time

600

-

ns

tDLCL

tHD:STA Start condition hold time

600

-

ns

tCHDH

tSU:STO Stop condition set up time

600

-

ns

tDHDL

tBUF

Time between Stop condition and next Start condition

1300

-

ns

tW

tWR

Write cycle time

-

5

ms

tNS(1)

-

Pulse width ignored (input filter on SCL and SDA) - single glitch

-

50

ns

tWU(1)

-

Wake up time(5)

-

5

μs

1. Evaluated by characterization – Not tested in production.

2. There are no minimum or maximum values for the input signal rise and fall times. It is however recommended by the I²C

specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz.

3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of

SDA.

4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that Rbus × Cbus time constant is within the values specified in Figure 16.

5. Wake up time: Delay between the VCCmin stable and the first accepted command.

M24256X-F

DC and AC parameters

DS12380 - Rev 2

page 29/42