SX28ACSLASHDP datasheet(28/51 Pages) PARALLAX

28 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 28 of 51

Rev 1.6 11/20/2006

12.0 RESET

Power-On Reset, Brown-Out Reset, Watchdog Reset, or

External Reset initializes the device. Each one of these

reset conditions causes the program counter to branch to

the top of the program memory. For example, on the

device with 2048 K

($800 hex) words of program

memory, the program counter is initialized to 07FF upon

a valid reset condition.

The device incorporates an on-chip Power-On Reset

(POR) circuit that generates an internal reset as VDD rises

during power-up. Figure 12-2 is a block diagram of the

circuit. The circuit contains a 10-bit Delay Reset Timer

(DRT) and a reset latch. The DRT controls the reset

timeout delay. The reset latch controls the internal reset

signal.

Upon power-up, the reset latch is set (device held in

reset), and the DRT starts counting once it detects a valid

logic high signal at the MCLR pin. Once DRT reaches the

end of the timeout period (typically 72 msec), the reset

latch is cleared, releasing the device from reset state.

Figure 12-1 shows a power-up sequence where MCLR is

not tied to the VDD pin and VDD signal is allowed to rise

and stabilize before MCLR pin is brought high. The

device will actually come out of reset TDRT msec after

MCLR goes high.

The brown-out circuitry resets the chip when device

power (VDD) dips below its minimum allowed value, but

not to zero, and then recovers to the normal value.

Figure 12-1: Time-Out Sequence on Power-Up

(MCLR not tied to Vdd)

Figure 12-2

Block Diagram

of On-Chip Reset Circuit

Note: Ripple counter is 10 bits for Power

on Reset (POR) only.

SX28AC/DP Datenblatt(PDF) 28 Page - Parallax Inc