SX28ACSLASHDP datasheet(17/51 Pages) PARALLAX

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Parallax SX20AC/SX28AC

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Page 17 of 51

Rev 1.6 11/20/2006

6.0

MEMORY ORGANIZATION

6.1.

Program Memory

The program memory is organized as 2K, 12-bit wide

words. The program memory words are addressed

sequentially by a binary program counter. The program

counter starts at zero. If there is no branch operation, it

will increment to the maximum value possible for the

device and roll over and begin again.

Internally, the program memory has a semi-transparent

page structure. A page is composed of 512 contiguous

program memory words. The lower nine bits of the

program counter are zeros at the first address of a page

and ones at the last address of a page. This page structure

has no effect on the program counter. The program

counter will freely increment through the page

boundaries.

6.1.1. Program Counter

The program counter contains the 11-bit address of the

instruction to be executed. The lower eight bits of the

program counter are contained in the PC register (02h)

while the upper bits come from the upper three bits of the

STATUS register (PA0, PA1, PA2). This is necessary to

cause jumps and subroutine calls across program memory

page boundaries. Prior to the execution of a branch

operation, the user program must initialize the upper bits

of the STATUS register to cause subsequent branch

instructions to vector to the desired page. An alternative

method is to use the PAGE instruction, which

automatically causes subsequent branch instructions to

branch vector to the desired page, based on the value

specified in the operand field. Upon reset, the program

counter is initialized with 07FFh.

6.1.2. Subroutine Stack

The subroutine stack consists of eight 11-bit save

registers. A physical transfer of register contents from the

program counter to the stack or vice versa, and within the

stack, occurs on all operations affecting the stack,

primarily calls and returns. The stack is physically and

logically separate from data RAM. The program cannot

read or write the stack.

6.2.

Data Memory

The data memory consists of 136 bytes of RAM,

organized as eight banks of 16 registers plus eight

registers which are not banked. Both banked and non-

banked memory locations can be addressed directly or

indirectly using the FSR (File Select Register). The

special-function registers are mapped into the data

memory.

6.2.1. File Select Register (04h)

Instructions that specify a register as the operand can only

express five bits of register address. This means that only

registers 00h to 1Fh can be accessed. The File Select

beyond 1Fh.

Figure 6-1 shows how FSR can be used to address RAM

locations. The three high-order bits of FSR select one of

eight SRAM banks to be accessed. The five low-order bits

select one of 32 SRAM locations within the selected

bank. FSR.4 essentially enables or disables banked RAM.

For the lower 16 addresses, Bank 0 is always accessed,

irrespective of the three high-order bits. Thus, RAM

they can always be accessed, regardless of the contents of

the FSR.

The entire data memory (including the dedicated-function

registers) consists of the lower 16 bytes of Bank 0 and the

upper 16 bytes of Bank 0 through Bank 7, for a total of

(1+8)*16 = 144 bytes. Eight of these bytes are for the

function registers, leaving 136 general-purpose memory

locations. In the 18-pin SX packages, register RC is not

used, which makes address 07h available as an additional

general-purpose memory location.

Below is an example of how to write to register 10h in

Bank 4:

mov

FSR,#$90

;Select Bank 4 by

;setting FSR<7:5>

mov

$10,#$64

;load register 10h with

;the literal 64h

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