SX28ACSLASHDP datasheet(32/51 Pages) PARALLAX

32 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 32 of 51

Rev 1.6 11/20/2006

15.4. RAM Addressing

Direct Addressing

The FSR register must initialized with an appropriate

value in order to address the desired RAM register. The

following table and code example show how to directly

access the banked registers.

Bank

FSR Value

010h

030h

050h

070h

090h

0B0h

0D0h

0F0h

mov

FSR,#$070

;Select RAM Bank 3

clr

$010

;Clear register 10h on

;Bank 3

mov

FSR,#$D0

;Select RAM Bank 6

clr

$010

;Clear register 10h on

;Bank 6

Indirect Addressing

To access any register via indirect addressing, simply

move the eight-bit address of the desired register into the

FSR and use INDF as the operand. The example below

shows how to clear all RAM locations from 10h to 1Fh in

all eight banks:

clr

FSR

;clear FSR to 00h (at addr 04h)

:loop setb SFR.4 ;set bit 4: addr 10h-1Fh,

;30-3Fh, etc

clr

INDF

;clear register pointed to by

;FSR

incsz

FSR

;increment FSR and test, skip

;jmp if 00h

jmp

:loop

;jump back and clear next

;register

15.5. The Bank Instruction

Often it is desirable to set the bank select bits of the FSR

provides this capability. This instruction sets the upper

bits of the FSR to point to a specific RAM bank without

affecting the other FSR bits. Example:

bank

$F0

;Select Bank 7 in FSR

inc

$1F

;increment file register

;1Fh in Bank 7

15.6.

Bit Manipulation

The instruction set contains instructions to set, reset, and

test individual bits in data memory. The device is capable

of bit addressing anywhere in data memory.

15.7. Input/Output Operation

The device contains three registers associated with each

I/O port. The first register (Data Direction Register),

configures each port pin as a Hi-Z input or output. The

second register (TTL/CMOS Register), selects the desired

input level for the input. The third register (Pull-Up

configured as a input. In addition to using the associated

port registers, appropriate values must be written into the

MODE register to configure the I/O ports.

When two successive read-modify-write instructions are

used on the same I/O port with a very high clock rate, the

“write” part of one instruction might not occur soon

enough before the “read” part of the very next instruction,

resulting in getting “old” data for the second instruction.

To ensure predictable results, avoid using two successive

read-modify-write instructions that access the same port

data register if the clock rate is high.

15.8. Increment/Decrement

The bank of 31 registers serves as a set of accumulators.

The instruction set contains instructions to increment and

decrement the register file. The device also includes both

INCSZ fr (increment file register and skip if zero) and

DECSZ fr (decrement file register and skip if zero)

instructions.

15.9. Loop Counting and Data Pointing

Testing

The device has specific instructions to facilitate loop

counting. The DECSZ fr (decrement file register and skip

if zero) tests any one of the file registers and skips the

next instruction (which can be a branch back to loop) if

the result is zero.

15.10. Branch and Loop Call Instructions

The device contains an 8-level hardware stack where the

return address is stored when a subroutine is called.

Multiple stack levels allow subroutine nesting. The

instruction set supports absolute address branching.

SX28AC/DP Datenblatt(PDF) 32 Page - Parallax Inc

SX28AC/DP Datenblatt(HTML) 32 Page - Parallax Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datenblatt Download

Link URL