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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PIC16F570 Datenblatt(PDF) 30 Page - Microchip Technology |
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PIC16F570 Datenblatt(HTML) 30 Page - Microchip Technology |
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30 / 129 page  PIC16F570 DS40001684E-page 30 2013-2014 Microchip Technology Inc. REGISTER 6-3: PORTC: PORTC REGISTER REGISTER 6-4: ANSEL REGISTER TABLE 6-4: REGISTERS ASSOCIATED WITH THE I/O PORTS R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 RC<7:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is <VIL max. TABLE 6-3: PORTC PINS ORDER OF PRECEDENCE Priority RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 1 C2IN- OP2 OP2- OP2+ OP1+ OP1- OP1 TRISC0 2 TRISC7 AN7 TRISC5 TRISC4 TRISC3 TRISC2 AN6 — 3 — TRISC6 — — — —TRISC1 — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ANS<7:0>: ADC Analog Input Pin Select bits(1,2) 0 = Analog function on selected ANx pin is disabled 1 = ANx configured as an analog input Note 1: When the ANSx bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin function previously defined, and the digital output drivers and input buffers will be also disabled. Exceptions exist when there is more than one analog function active on the ANx pin. It is the user’s responsibility to ensure that the ADC loading on the other analog functions does not affect their application. 2: The ANS<7:0> bits are active regardless of the condition of ADON. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on MCLR and WDT Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 06h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu 07h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 08h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’ |
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