PIC16F570 datasheet(54/129 Pages) MICROCHIP

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PIC16F570

DS40001684E-page 54

 2013-2014 Microchip Technology Inc.

9.0

ANALOG-TO-DIGITAL (A/D)

CONVERTER

The A/D Converter allows conversion of an analog

signal into an 8-bit digital signal.

9.1

Clock Divisors

The ADC has four clock source settings ADCS<1:0>.

There are three divisor values 16, 8 and 4. The fourth

setting is INTOSC with a divisor of four. These settings

will allow a proper conversion when using an external

oscillator at speeds from 20 MHz to 350 kHz. Using an

external oscillator at a frequency below 350 kHz

requires the ADC oscillator setting to be INTOSC/4

(ADCS<1:0> = 11) for valid ADC results.

The ADC requires 13 TAD periods to complete a

conversion. The divisor values do not affect the number

of TAD periods required to perform a conversion. The

divisor values determine the length of the TAD period.

When the ADCS<1:0> bits are changed while an ADC

conversion is in process, the new ADC clock source will

not be selected until the next conversion is started. This

clock source selection will be lost when the device

enters Sleep.

9.1.1

VOLTAGE REFERENCE

There is no external voltage reference for the ADC. The

ADC reference voltage will always be VDD.

9.1.2

ANALOG MODE SELECTION

The ANS<7:0> bits are used to configure pins for

analog input. Upon any Reset, ANS<7:0> defaults to

FF. This configures the affected pins as analog inputs.

Pins configured as analog inputs are not available for

digital output. Users should not change the ANS bits

while a conversion is in process. ANS bits are active

regardless of the condition of ADON.

9.1.3

ADC CHANNEL SELECTION

The CHS bits are used to select the analog channel to

be sampled by the ADC. The CHS<3:0> bits can be

changed at any time without adversely effecting a con-

version. To acquire an external analog signal, the

CHS<3:0> selection must match one of the pin(s)

selected by the ANS<7:0> bits. When the ADC is on

(ADON = 1) and a channel is selected that is also being

used by the comparator, then both the comparator and

the ADC will see the analog voltage on the pin.

When the CHS<3:0> bits are changed during an ADC

conversion, the new channel will not be selected until

the current conversion is completed. This allows the

current conversion to complete with valid results. All

channel selection information will be lost when the

device enters Sleep.

9.1.4

THE GO/DONE BIT

The GO/DONE bit is used to determine the status of a

conversion, to start a conversion and to manually halt a

conversion in process. Setting the GO/DONE bit starts

a conversion. When the conversion is complete, the

ADC module clears the GO/DONE bit and sets the

ADIF bit in the INTCON0 register.

A conversion can be terminated by manually clearing

the GO/DONE bit while a conversion is in process.

Manual termination of a conversion may result in a

partially converted result in ADRES.

The GO/DONE bit is cleared when the device enters

Sleep, stopping the current conversion. The ADC does

not have a dedicated oscillator, it runs off of the

instruction clock. Therefore, no conversion can occur in

Sleep.

The GO/DONE bit cannot be set when ADON is clear.

9.1.5

A/D ACQUISITION REQUIREMENTS

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-1. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-1.

The maximum recommended impedance for analog

sources is 10 k

. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (256 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

Note:

The ADC clock is derived from the

instruction clock. The ADCS divisors are

then applied to create the ADC clock

Note:

It is the user’s responsibility to ensure that

the use of the ADC and op amp

simultaneously on the same pin does not

adversely

affect

the

signal

being

monitored or adversely effect device

operation.

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