PIC16F570 datasheet(49/129 Pages) MICROCHIP

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DS40001684E-page 49

PIC16F570

8.10

Power-down Mode (Sleep)

A device may be powered down (Sleep) and later

Powered-up (wake-up from Sleep).

8.10.1

SLEEP

The Power-Down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit of the STATUS register is set,

the PD bit of the STATUS register is cleared and the

oscillator driver is turned off. The I/O ports maintain the

status they had before the SLEEP instruction was

executed (driving high, driving low or high-impedance).

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level if MCLR is

enabled.

8.10.2

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of

the following events:

An external Reset input on MCLR/VPP pin.

A Watchdog Timer Time-out Reset (if WDT was

enabled).

From an interrupt source, see Section 8.11

“Interrupts” for more information.

On waking from Sleep, the processor will continue to

execute the instruction immediately following the

SLEEP instruction. If the WUR bit is also set, upon

waking from Sleep, the device will reset. If the GIE bit

is also set, upon waking from Sleep, the processor will

branch

the

interrupt

vector.

Please

see

Section 8.11 “Interrupts” for more information.

The TO and PD bits can be used to determine the

cause of the device Reset. The TO bit is cleared if a

WDT time-out occurred and subsequently caused a

wake-up. The PD bit, which is set on power-up, is

cleared when SLEEP is invoked.

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

8.11

Interrupts

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

These following interrupt sources are available on the

PIC16F570 device:

• Timer0 Overflow

• ADC Completion

• Comparator Output Change

• Interrupt-on-change pin

Refer to the corresponding chapters for details.

8.11.1

OPERATION

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON0 register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

The enable bits for specific interrupts can be found in

the INTCON1 register. An interrupt is recorded for a

specific interrupt via flag bits found in the INTCON0

The ADC Conversion flag and the Timer0 Overflow

flags will be set regardless of the status of the GIE and

individual interrupt enable bits.

The Comparator and Interrupt-on-change flags must

be enabled for use. One or both of the comparator

outputs can be enabled to affect the interrupt flag by

setting the C1WU bit in the CM1CON0 register and the

C2WU bit in the CM2CON0 register. The Interrupt-on-

change flag is enabled by setting the RBWU bit in the

OPTION register.

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

CAUTION: Right before entering Sleep, read the

input pins. When in Sleep, wake-up

occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before

re-entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

CAUTION: Right before entering Sleep, read the

comparator

Configuration

CM1CON0 and CM2CON0. When in

Sleep, wake-up occurs when the com-

parator output bit C1OUT and C2OUT

change from the state they were in at the

last reading. If a wake-up on comparator

change occurs and the pins are not read

before re-entering Sleep, a wake-up will

occur immediately, even if no pins

change while in Sleep mode.

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