PIC16F570 datasheet(64/129 Pages) MICROCHIP

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PIC16F570

DS40001684E-page 64

 2013-2014 Microchip Technology Inc.

11.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The Comparator Voltage Reference module also

allows the selection of an internally generated voltage

reference for one of the C2 comparator inputs. The

VRCON register (Register 11-1) controls the voltage

reference module shown in Figure 11-1.

11.1

Configuring the Voltage Reference

The voltage reference can output 32 voltage levels; 16

in a high range and 16 in a low range.

Equation 11-1 determines the output voltages:

EQUATION 11-1:

11.2

Voltage Reference Accuracy

The full range of VSS to VDD cannot be realized due to

construction of the module. The transistors on the top

and bottom of the resistor ladder network (Figure 11-1)

keep CVREF from approaching VSS or VDD. The

exception is when the module is disabled by clearing

the VREN bit of the VRCON register. When disabled,

the reference voltage is VSS when VR<3:0> is ‘0000’

and the VRR bit of the VRCON register is set. This

allows the comparator to detect a zero-crossing and

not consume the CVREF module current.

The voltage reference is VDD derived and, therefore,

the CVREF output changes with fluctuations in VDD. The

tested absolute accuracy of the comparator voltage

reference can be found in Section 15.0 “Electrical

Characteristics”.

VRR = 1 (low range):

VRR = 0 (high range):

CVREF = (VDD/4) + (VR<3:0> x VDD/32)

CVREF = (VR<3:0>/24) x VDD

VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

R/W-1

VREN

VROE1

VROE2

VRR

VR3

VR2

VR1

VR0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

VREN: CVREF Enable bit

1 = CVREF is powered on

0 = CVREF is powered down, no current is drawn

bit 6

VROE1: CVREF1 Output Enable bit(1)

1 = CVREF1 output is enabled

0 = CVREF1 output is disabled

bit 5

VROE2: CVREF2 Output Enable bit(1)

1 = CVREF2 output is enabled

0 = CVREF2 output is disabled

bit 4

VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 3-0

VR<3:0> CVREF Value Selection bits

When VRR = 1: CVREF= (VR<3:0>/24)*VDD

When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD

Note 1: When this bit is set, the TRIS for the CVREFX pin is overridden and the analog voltage is placed on the

CVREFX pin.

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