PIC16F570 datasheet(32/129 Pages) MICROCHIP

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PIC16F570

DS40001684E-page 32

 2013-2014 Microchip Technology Inc.

7.0

TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit of the

OPTION register. In Timer mode, the Timer0 module

will increment every instruction cycle (without pres-

caler). If TMR0 register is written, the increment is

inhibited for the following two cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

There are two types of Counter mode. The first Counter

mode uses the T0CKI pin to increment Timer0. It is

selected by setting the T0CS bit of the OPTION

every rising or falling edge of pin T0CKI. The T0SE bit

of the OPTION register determines the source edge.

Clearing the T0SE bit selects the rising edge.

Restrictions on the external clock input are discussed

in detail in Section 7.1 “Using Timer0 with an

External Clock”.

The second Counter mode uses the output of the

comparator to increment Timer0. It can be entered in by

setting the T0CS bit of the OPTION register, and

clearing the C1T0CS bit of the CM1CON0 register

(C1OUTEN [CM1CON0<6>] does not affect this mode

of operation). This enables an internal connection

between the comparator and the Timer0.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA of the OPTION register. Clearing the

PSA bit will assign the prescaler to Timer0. The pres-

caler is not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 7.2 “Prescaler”

details the operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 7-1.

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register (see Register 4-2).

2: The prescaler is shared with the Watchdog Timer.

3: The C1T0CS bit is in the CM1CON0 register.

T0CKI

T0SE(1)

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks

TMR0 Reg

PSOUT

(2-cycle delay)

PSOUT

Data Bus

PSA(1)

PS2(1), PS1(1), PS0(1)

Sync

Comparator

Output

C1T0CS(3)

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