LP5521 datasheet(21/51 Pages) TI2

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ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C SLAVE address (chip address)

LP5521

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SNVS441I – JANUARY 2007 – REVISED NOVEMBER 2016

Product Folder Links: LP5521

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Figure 22. I2C Chip Address

7.5.1.6 Control Register Write Cycle

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master will send further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

7.5.1.7 Control Register Read Cycle

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

ADDRESS MODE

Data Read

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register address possible

Data Write

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register address possible

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