LP5521 datasheet(33/51 Pages) TI2

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LP5521

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SNVS441I – JANUARY 2007 – REVISED NOVEMBER 2016

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7.6.9 Configuration Control (CONFIG)

Address 08H

Reset value 00H

Table 29. CONFIG Register

PWM_HF

PWRSAVE_EN

CP_MODE[1:0]

R_TO_BATT

CLK_DET_EN

INT_CLK_EN

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

PWM_HF

R/W

High

PWM clock

0 = 256 Hz PWM clock used (CLK_32K)

1 = 558 Hz PWM clock used (internal oscillator)

PWRSAVE_EN

R/W

High

Power save mode enable

CP_MODE

4:3

R/W

Charge pump operation mode

00b = OFF

01b = Forced to bypass mode (1x)

10b = Forced to 1.5x mode

11b = Automatic mode selection

R_TO_BATT

R/W

High

R channel supply connection

0 = R output connected to charge pump

1 = R output connected to battery

CLK_DET_EN,

INT_CLK_EN

1:0

R/W

LED Controller clock source

00b = External clock source (CLK_32K)

01b = Internal clock

10b = Automatic selection

11b = Internal clock

7.6.10 R Channel Program Counter Value (R Channel PC)

Address 09H

Reset value 00H

Table 30. R Channel PC Register

R_PC[3]

R_PC[2]

R_PC[1]

R_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

R_PC

3:0

R/W

R channel program counter value

PC registers are synchronized to a 32-kHz clock. Delay between consecutive I2C writes to PC registers needs to

be longer than 153 μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

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