LP5521 datasheet(29/51 Pages) TI2

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LP5521

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SNVS441I – JANUARY 2007 – REVISED NOVEMBER 2016

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7.6.1 Enable Register (Enable)

Address 00H

Reset value 00H

Table 21. Enable Register

LOG_EN

CHIP_EN

R_EXEC[1]

R_EXEC[0]

G_EXEC[1]

G_EXEC[0]

B_EXEC[1]

B_EXEC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

LOG_EN

R/W

High

Logarithmic PWM adjustment generation enable

CHIP_EN

R/W

High

Master chip enable. Enables device internal startup sequence. Startup delay

after setting CHIP_EN is 500 μs. See Operation for further information.

Setting EN pin low resets the CHIP_EN state to 0.

R_EXEC

5:4

R/W

R channel program execution.

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current R channel PC value,

increment PC and change R_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current R Channel PC

value

11b = Execute instruction defined by current R channel PC value and change

R_EXEC to 00b (Hold)

G_EXEC

3:2

R/W

G channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current G channel PC value,

increment PC and change G_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current G Channel PC

value

11b = Execute instruction defined by current G channel PC value and

change G_EXEC to 00b (Hold)

B_EXEC

1:0

R/W

B channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC

mode is hold. PC can be read or written only in this mode.

01b = Step: Execute instruction defined by current B channel PC value,

increment PC and change B_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current B Channel PC

value

11b = Execute instruction defined by current B channel PC value and change

B_EXEC to 00b (Hold)

EXEC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to ENABLE register

(00H) need to be longer than 488 μs (typ).

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