LP5521 datasheet(8/51 Pages) TI2

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LP5521

SNVS441I – JANUARY 2007 – REVISED NOVEMBER 2016

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Logic Interface Characteristics (continued)

(V(EN) = 1.65 V...VDD, and limits apply through ambient temperature range –30°C < TA < +85°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT SCL, SDA, TRIG, CLK_32K

VIL

Input low level

0.2 × V(EN)

VIH

Input high level

0.8 × V(EN)

Input current

–1

µA

ƒCLK_32K

Clock frequency

TJ = 25°C

kHz

ƒSCL

Clock frequency

400

kHz

LOGIC OUTPUT SDA, TRIG, INT

IOUT = 3 mA (pullup current),

TJ = 25°C

0.3

VOL

Output low level

IOUT = 3 mA (pull-up current)

0.5

Output leakage current

µA

LOGIC INPUT ADDR_SEL0, ADDR_SEL1

VIL

Input low level

0.2 × VDD

VIH

Input high level

0.8 × VDD

Input current

–1

µA

LOGIC OUTPUT GPO, INT (IN GPO STATE)

IOUT = 3 mA, TJ = 25°C

0.3

VOL

Output low level

IOUT = 3 mA

0.5

TJ = 25°C

VDD – 0.3

VOH

Output high level

IOUT = –2 mA

VDD – 0.5

Output leakage current

µA

(1)

Verified by design.

6.9 I

2C Timing Requirements (SDA, SCL)

Limits are for TJ = 25°C

(1)

MIN

MAX

UNIT

ƒSCL

Clock frequency

400

kHz

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup time for a repeated START condition

600

Data hold time

Data set-up time

100

Rise time of SDA and SCL

20+0.1Cb

300

Fall time of SDA and SCL

15+0.1Cb

300

Set-up time for STOP condition

600

Bus-free time between a STOP and a START condition

1.3

µs

Capacitive load for each bus line

200

Figure 1. I2C Timing Diagram

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