CC1010-RTY1 datasheet(64/150 Pages) TI2

64 / 150 page

CC1010

SWRS047A

Page 64 of 146

System clock

Watchdog Prescaler

WDTPRE(1:0)

8 Bit Watchdog Counter

WDTEN

System

Reset

Clear

Enable

WDTCLR

Figure 14. Watchdog Timer

Setting

different

prescaler

settings,

combined

with

different

Main

Crystal

Oscillator frequencies, generates reset at

an interval of:

system

WDTPRE

)

(

256

⋅

The

intervals

for

the

maximum

and

minimum clock frequencies are shown in

Table 21 below.

WDTPRE.1

WDTPRE.0

Division Rate

Reset timing, given

fXOSC = 3MHz

Reset timing, given

fXOSC = 24MHz

2048

175 ms

21.8 ms

4096

350 ms

43.7 ms

8192

699 ms

87.4 ms

16384

1400 ms

175 ms

Table 21. Watchdog Timer timing

16.5.1

Disabling the Watchdog Timer

The Watchdog Timer is enabled after

system reset, through the Watchdog Timer

enable flag WDT.WDTEN. To disable the

Watchdog

Timer,

this

flag

must

cleared.

However,

clearing

this

flag

requires the user to first set the flag

WDT.WDTSE

and

then

clearing

WDT.WDTEN

within

system

clock

periods (preferably in the next instruction).

If interrupts are enabled while disabling

the Watchdog Timer, the user must make

sure that WDT.WDTEN is actually cleared.

This could for instance be done as follows:

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