CC1010-RTY1 datasheet(72/150 Pages) TI2

72 / 150 page

CC1010

SWRS047A

Page 72 of 146

SPCR (0xA1) - SPI Control Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 0

R/W

Reserved, write 0

SPE

R/W

SPI Enable.

0 : SPI interface is disabled

1 : SPI interface is enabled

DORD

R/W

Data Order

0 : Least significant bit (LSB) is transmitted / received first

1 : Most significant bit (MSB) is transmitted / received first

CPOL

R/W

Clock Polarity

0 : SCK has negative clock polarity

1 : SCK has positive clock polarity

CPHA

R/W

Clock Phase

0 : Data is output on DO when SCK goes from CPOL to

CPOL

and is sampled from DI when SCK goes from

CPOL

to CPOL

1 : Data is output on DO when SCK goes from CPOL to

CPOL

and is sampled from DI when SCK goes from

CPOL

to CPOL

1:0

SPR(1:0)

R/W

SPI Data Rate.

SPR(1:0)

00 : SCK clock frequency = fXOSC / 8

01 : SCK clock frequency = fXOSC / 16

10 : SCK clock frequency = fXOSC / 32

11 : SCK clock frequency = fXOSC / 64

SPDR (0xA2) - SPI Data Register

Bit

Name

R/W

Reset value

Description

7:0

SPDR(7:0)

R/W

0x00

SPI Data Register

Writing to SPDR when SPCR.SPE is set will initiate a

data transmission. Reading SPDR will read the data

input buffer, which is only updated after each completed

transmission.

SPSR (0xA3) - SPI Status Register

Bit

Name

R/W

Reset value

Description

7:2

0x00

Reserved, read as 0

SPA

SPI Active status bit

0 : The SPI interface is currently not transmitting data

1 : The SPI interface is currently transmitting data

WCOL

Write collision flag. This flag is updated by hardware

when SPDR is written.

0 : The previous write to SPDR did not generate a data

collision.

1 : The previous write to SPDR generated a data

collision

Writing data to SPDR when SPCR.SPE is

set will initiate a data transmission. 8 bits

are transmitted and received with the data

order, clock polarity, clock phase and data

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