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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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TMS320VC5421 Datenblatt(PDF) 71 Page - Texas Instruments |
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TMS320VC5421 Datenblatt(HTML) 71 Page - Texas Instruments |
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71 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 71 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) switching characteristics for the McBSP† [H=0.5tc(CO)] (see Figure 39 and Figure 40) PARAMETER MIN MAX UNIT tc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4H ns tw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D–4‡ D+1‡ ns tw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C–4‡ C+1‡ ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR int –3 3 ns t Delay time BCLKX high to internal BFSX valid BCLKX int –3 8 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX ext 2 15 ns t Disable time BCLKX high to BDX high impedance following last data bit BCLKX int –8 5 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit BCLKX ext 1 19 ns Delay time, BCLKX high to BDX valid. This applies to all bits except the first BCLKX int 0 11 Delay time, BCLKX high to BDX valid. This a lies to all bits exce t the first bit transmitted. BCLKX ext 5 20 t § DXENA 0 BCLKX int 11 ns td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid.§ Only applies to first bit transmitted when in Data Delay 1 DXENA = 0 BCLKX ext 20 ns Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA 1 BCLKX int 25 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 BCLKX ext 27 § DXENA 0 BCLKX int –4 t Enable time, BCLKX high to BDX driven.§ Only applies to first bit transmitted when in Data Delay 1 DXENA = 0 BCLKX ext 2 ns ten(BCKXH-BDX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA 1 BCLKX int 6 ns or 2 (XDATDLY=01b or 10b) modes DXENA = 1 BCLKX ext 12 § DXENA 0 BFSX int 9 t Delay time, BFSX high to BDX valid.§ Only applies to first bit transmitted when in Data Delay 0 DXENA = 0 BFSX ext 12 ns td(BFXH-BDXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA 1 BFSX int 25 ns (XDATDLY=00b) mode. DXENA = 1 BFSX ext 26 § DXENA 0 BFSX int –1 t Enable time, BFSX high to BDX driven.§ Only applies to first bit transmitted when in Data Delay 0 DXENA = 0 BFSX ext 2 ns ten(BFXH-BDX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode DXENA 1 BFSX int 9 ns (XDATDLY=00b) mode DXENA = 1 BFSX ext 13 † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ T=BCLKRX period = (1 + CLKGDV) * 2H C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § See the TMS320C54x Enhanced Peripherals Reference Set, Volume 5 (literature number SPRU302) for a description of the DX enable (DXENA) and data delay features of the McBSP. |
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