TMS320VC5421 datasheet(72/88 Pages) TI

72 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial port timing (continued)

(n–2)

Bit (n–1)

(n–3)

(n–2)

Bit (n–1)

(n–4)

(n–3)

(n–2)

Bit (n–1)

th(BCKRL–BDRV)

tsu(BDRV–BCKRL)

th(BCKRL–BDRV)

tsu(BDRV–BCKRL)

th(BCKRL–BDRV)

th(BCKRL–BFRH)

tsu(BFRH–BCKRL)

td(BCKRH–BFRV)

tr(BCKRX)

tw(BCKRXL)

tc(BCKRX)

tw(BCKRXH)

(RDATDLY=10b)

BDR

(RDATDLY=01b)

BDR

(RDATDLY=00b)

BDR

BFSR (ext)

BFSR (int)

BCLKR

Figure 39. McBSP Receive Timings

ten(BCKXH–BDX)

td(BCKXH–BDXV)

ten(BCKXH–BDX)

tdis(BCKXH–BDXHZ)

td(BCKXH–BDXV)

td(BFXH–BDXV)

ten(BDFXH–BDX)

(XDATDLY=10b)

BDX

(XDATDLY=01b)

BDX

(XDATDLY=00b)

BDX

(n–2)

Bit (n–1)

Bit 0

(n–4)

Bit (n–1)

(n–3)

(n–2)

Bit 0

(n–3)

(n–2)

Bit (n–1)

Bit 0

th(BCKXL–BFXH)

tf(BCKRX)

tr(BCKRX)

tw(BCKRXL)

tc(BCKRX)

tw(BCKRXH)

BFSX (ext)

BFSX (int)

BCLKX

td(BCKXH–BFXV)

tsu(BFXH–BCKXL)

Figure 40. McBSP Transmit Timings

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