TMS320VC5421 datasheet(17/88 Pages) TI

17 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory

Each ’5421 DSP subsystem maintains the peripheral register memory map and interrupt location/priorities of

the standard ’5420. Figure 2 shows the size of the required memory blocks and their link map within the program

and data space of the cLEAD core. The total on-chip memory for the ’5421 devices is 256K-word data/program.

Memory-

Mapped

Registers

On-Chip

DARAM A/B§

(32K Words)

Prog/Data

On-Chip

SARAM A/B

(32K Words)

Data Only

(DROM=1)

External

(DROM=0)

00 0000

00 005F

00 0060

00 7FFF

00 8000

00 FFFF

On-Chip

DARAM A/B§

(32K Words)

Prog/Data

(OVLY=1)

On-Chip

Shared

DARAM 0

(24K Words)

Prog Only

00 0000

00 7FFF

00 8000

00 FFFF

Data

Hex

Program Page 0

Hex

External

(OVLY=0)

On-Chip

DARAM A/B§

(32K Words)

Prog/Data

(OVLY=1)

On-Chip

Shared

DARAM 1

(32K Words)

Prog Only

01 0000

01 FFFF

Program Page 1

Hex

External

(OVLY=0)

On-Chip

DARAM A/B§

(32K Words)

Prog/Data

(OVLY=1)

On-Chip

Shared

DARAM 2

(32K Words)

Prog Only

02 0000

02 FFFF

Program Page 2

Hex

External

(OVLY=0)

(extended)

On-Chip

DARAM A/B§

(32K Words)

Prog/Data

(OVLY=1)

On-Chip

Shared

DARAM 3

(32K Words)

Prog Only

03 0000

03 FFFF

Program Page 3

Hex

External

(OVLY=0)

(extended)

0n 0000

0n FFFF

Program Page n

Hex

External‡

ROM

(ROMEN=1)†

02 7FFF

02 8000

03 7FFF

03 8000

0n 7FFF

0n 8000

External‡

01 7FFF

01 8000

00 DFFF

00 E000

00 F7FF

00 F800

(n = 4 – 127)

Shared 0

Shared 1

Shared 2

Shared 3

00 005F

00 0060

01 005F

01 0060

02 005F

02 0060

03 005F

03 0060

0n 005F

0n 0060

Reserved

† ROM enabled after reset.

‡ When cLEAD PMST register bit MP/MC=0 and an address is generated outside the on-chip memory bound or the address reach, i.e.,

XPC > 3h, access is always external, if XIO = 1. Pages 8–127 are mapped over pages 4–7. When XIO = 1 and MP/MC = 1, program pages 0,

1, 2, and 3 are external. Pages 4–127 are mapped over pages 0–3.

§ On-chip DARAM A and SARAM A are for core A. Likewise, on-chip DARAM B and SARAM B are for core B.

NOTES: A. Clearing the ROMEN bit (GPIO[7]) enables an 8K-word block (0E000h – 0FFFFh) of DARAM .

B. All external accesses require the XIO pin to be high.

C. CPU I/O space is a single page of 64K words. Access is always external.

D. All internal memory is divided into 8K blocks.

Figure 2. Memory Map Relative to CPU Subsystems A and B

on-chip dual-access RAM (DARAM)

The ’5421 subsystems A and B each have 32K 16-bit words of on-chip DARAM (4 blocks of 8K words). Each

of these DARAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store

data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory

space. The DARAM can be mapped into program/data memory space by setting the OVLY bit in the

processor-mode status (PMST) register of the 54X cLEAD CPU in each DSP subsystem.

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