TMS320VC5421 datasheet(27/88 Pages) TI

27 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multichannel buffered serial port (McBSP)

The ’5421 device provides high-speed, full-duplex serial ports that allow direct interface to other ’C54x/’LC54x

devices, codecs, and other devices in a system. There are six multichannel buffered serial ports (McBSPs) on

board (three per subsystem).

The McBSP provides:

D Full-duplex communication

D Double-buffer data registers, which allow a continuous data stream

D Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D Direct interface to:

–

T1/E1 framers

–

MVIP switching-compatible and ST-BUS compliant devices

–

IOM-2 compliant device

–

AC97-compliant device

–

Serial port interface (SPI

D Multichannel transmit and receive of up to 128 channels

D A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits

D µ-law and A-law companding

D Programmable polarity for both frame synchronization and data clocks

D Programmable internal clock and frame generation

The ’5421 McBSPs have been enhanced to provide more flexibility in the choice of the sample rate generator

input clock source. On previous C5000 devices, the McBSP sample rate input clock can be driven from one of

two possible choices: the internal CPU clock , or the external CLKS pin. However, most C5000 devices have

only the internal CPU clock as a possible source because the CLKS pin is not implemented on most device

packages.

To accomodate applications that require an external reference clock for the sample rate generator, the ’5421

McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the

input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control

bit 13 – McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in

the McBSPs on previous C5000 devices. The new bit layout of the PCR is shown in Figure 8. For a description

of the remaining bits, see

TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature

number SPRU302).

Reserved

XIOEN

RIOEN

FSXM

FSRM

CLKXM

CLKRM

R,+0

RW,+0

765

SCLKME

CLKS_STAT

DX_STAT

DR_STAT

FSXP

FSRP

CLKXP

CLKRP

RW,+0

R,+0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset

Figure 8. Pin Control Register (PCR)

SPI is a trademark of Motorola Incorporated.

TMS320VC5421 Datenblatt(PDF) 27 Page - Texas Instruments

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