TMS320VC5421 datasheet(21/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

software-programmable wait-state generators

The software-programmable wait-state generator can be used to extend external bus cycles up to fourteen

machine cycles to interface with slower off-chip memory and I/O devices. The software wait-state register

(SWWSR) controls the operation of the wait-state generator. The SWWSR of a particular DSP subsystem

(A or B) is used for the external memory interface, depending on the state of the xDMA/XIO arbitration logic (see

Direct Memory Access (DMA) Controller section and Table 13. The 14 least significant bits (LSBs) of the

SWWSR specify the number of wait states (0–7) to be inserted for external memory accesses to five separate

address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)

defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized

to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3

and described in Table 4.

XPA

I/O

Data

Program

R/W=0

R/W=111

LEGEND: R = Read, W = Write

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

Table 4. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

XPA

Extended program address control bit. XPA is used in conjunction with the program space fields

(bits 0 through 5) to select the address range for program space wait states.

14–12

I/O

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses

within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

the base number of wait states.

11–9

Data

Upper data space. The field value (0–7) corresponds to the base number of wait states for external data

space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

8–6

Data

Lower data space. The field value (0–7) corresponds to the base number of wait states for external data

space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

5–3

Program

Upper program space. The field value (0–7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

- XPA = 0: x8000–xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

2–0

Program

Program space. The field value (0–7) corresponds to the base number of wait states for external program

space accesses within the following addresses:

- XPA = 0: x0000–x7FFFh

- XPA = 1: 00000–3FFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the

base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described

in Table 5.

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