TMS320VC5421 datasheet(23/88 Pages) TI

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TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programmable bank-switching (continued)

Table 6. BSCR Register Bit Functions for Each DSP Subsystem

BIT

NO.

BIT

NAME

RESET

VALUE

FUNCTION

15–12

BNKCMP

1111

Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four

most significant bits (MSBs) of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15)

are compared, resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

PS-DS

Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of

program read and data read or data read and program read.

PS-DS = 0

No extra cycles are inserted by this feature.

PS-DS = 1

One extra cycle is inserted between consecutive data and program reads.

10–9

Reserved

These bits are reserved and are unaffected by writes.

IPIRQ

The IPIRQ bit is used to send an interprocessor interrupt to the other subsystem. IPIRQ=1 sends the

interrupt. IPIRQ must be cleared before subsequent interrupts can be made. Refer to the interrupts section

for more details.

7–3

Reserved

These bits are reserved and are unaffected by writes.

Bus holder. BH controls the data bus holder feature: BH is cleared to 0 at reset.

BH = 0

The bus holder is disabled.

BH = 1

The bus holder is enabled. When not driven, the data bus (PPD[15:0]) is held in the

previous logic level.

Reserved

This bit is reserved and is unaffected by writes.

EXIO

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

The external bus interface functions as usual.

EXIO = 1

The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the

HM bit of ST1 cannot be modified when the interface is disabled.

parallel I/O ports

The ’5421 has a total of 64K words of I/O port address space. These ports can be addressed by PORTR and

PORTW. The IS signal indicates the read/write access through an I/O port. The devices can interface easily with

external devices through the I/O ports while requiring minimal off-chip address-decoding logic. The SELA/B pin

selects which subsystem is accessing the external I/O space.

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