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AM7968-125JC Datenblatt(PDF) 104 Page - Advanced Micro Devices |
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AM7968-125JC Datenblatt(HTML) 104 Page - Advanced Micro Devices |
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104 / 127 page ![]() AMD 100 TAXIchip Integrated Circuits Technical Manual TAXI Technical Information Publication #89-06 Subject: TAXl for FDDI Applications? Question: Can the TAXIchip set be used for FDDI physical layer applications? Answer: The TAXIchip set is code compatible with the FDDI physical layer but there are restric- tions in the design which would cause difficulty in using the TAXIchip set for the physical layer of an FDDI node. The TAXIchip set by itself cannot be used to build a fully compliant FDDI node, although it provides several of the functions required. The TAXI Transmitter is compatible with FDDI at the physical layer electrical interface and can send all codes specified by FDDI. An exception to the encoding is that Quiet- Line-State (QLS) is defined as fiber-dark for FDDI, requiring a static SEROUT=LOW, and the Transmitter defines the equivalent of QLS, as Command F, as no-transitions, with no control of the static logical state. The TAXI Receiver is also compatible with FDDI at the physical layer electrical interface and can recognize the codes specified by FDDI, with restrictions. The restrictions concern Master-Line-State (MLS), Halt-Line-State (HLS), and the carrier detect function. MLS and HLS are terms describing a data stream composed of a consecutive string of HQ and HH symbols respectively, representing a line-state condition. The Receiver will decode these symbols, but it does not count them to signal line-states as required by FDDI. MLS and HLS are relatively long run-length signals with 10 and 5 bit-times between transitions respectively, as compared to a maximum limit of 3 bit-times for data. The Receiver PLL was designed for wide operating frequency range, with tradeoffs in the ability and time required to capture long run-length data sequences. The FDDI specifica- tion allows 100 µs for the Receiver to lock upon and detect MLS following a long period of QLS. A typical TAXI Receiver will meet these criteria but the production parts are neither tested nor guaranteed for this condition. There are no problems associated with tracking the MLS signal once the PLL has acquired lock. HQ and HH, within the TAXI Receiver, require proper byte framing for detection. MLS and HLS as specified by FDDI are not framed, therefore the transition may be located at any of the ten bit locations. The result, as decoded within the TAXI Receiver, will be as follows: MLS: 00100 00000 = HQ CMD-A 10% probability 00000 00100 = QH CMD-D 10% probability all other = Violation 80% probability HLS: 00100 00100 = HH CMD-8 20% probability all other = Violation 80% probability The FDDI line state definition does not preclude the insertion of an occasional sync into the MLS or HLS data stream for proper framing, solving the recognition problem. If full FDDI compliance is required, MLS and HLS must be detected external to the TAXIchip set. The carrier detect function, as specified by FDDI, requires the flagging of a QLS to the MAC layer as long as the fiber is dark. The TAXI SERIN inputs must be static for this condition to be met by the TAXI Receiver. This problem must be addressed directly by the Optical receiver or gating of its outputs. Functions of the FDDI MAC layer interface are not directly addressed in the TAXI designs. |
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