AM7968-125JC datasheet(107/127 Pages) AMD

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TAXIchip Integrated Circuits Technical Manual

TAXI Technical Information Publication #89-10

Subject: TAXI Receiver CSTRB and DSTRB Pulse Width

Question:

What is the maximum CSTRB and DSTRB pulse width?

Answer:

The internal logic of the TAXI Receiver determines the pulse width of CSTRB and

DSTRB based on the timing of an internal clock (Bit Clock). Under normal conditions,

the pulse width will be 4-bit times wide in the 8-bit mode, and 5-bit times wide in the

9- and 10-bit modes. An exception to this typical width is upon re-sync which can cause

the pulse to be expanded by up to 5 bit times as the byte boundaries are re-aligned to

the incoming data stream.

The number of bit times used to represent data differs based on the operational mode;

in 8-bit mode, data is encoded into 10 bits, in 9-bit mode 11-bits, and in 10-bit mode

2 bits. For example, a Receiver operating with a 12.5 MHz crystal and utilizing 8-bit

mode will have a clock period of 80 ns (1/12.5 MHz = 80 ns). Internally the Receiver

divides this period by 10, forming the internal bit boundaries used to represent the

encoded data. This example yields a 8 ns (80 ns/10 = 8 ns) bit period, which translates

to a internal clock rate of 125 MHz (1/8 ns = 125 MHz). Figure 11. shows a timing

diagram of a TAXI Receiver internal clock and its relationship to CLK, Data, and Strobe

outputs. The Receiver utilizes this divided clock to define its internal logic states.

The CSTRB and DSTRB signals are generated by using these logic states and have a

fixed relationship to the incoming encoded data. The figure shows that from the

beginning of the byte (state 0), the CSTRB or DSTRB delay is two internal clock periods

before going high, and the signal remains high for four internal clock periods then

returns to a low logic level. Actual pulse width will vary from this ideal width due to signal

rise and fall delay, propagation delay and effects of loads external to the Receiver. The

data sheet parameters reflect these delays and normal manufacturing guard bands.

AM7968-125JC Datenblatt(PDF) 107 Page - Advanced Micro Devices