AM7968-125JC datasheet(109/127 Pages) AMD

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TAXIchip Integrated Circuits Technical Manual

TAXI Technical Information Publication #89-11

Subject: Using Receiver CLK Output to Run a TAXI Transmitter

Question:

Is it possible to use the Receiver CLK output to drive the X1 input of a TAXI Transmitter?

Answer:

To assure accurate transmission of data, the Transmitter must have a stable, jitter free,

byte rate reference to its multiplying PLL. This is typically derived from a crystal and can

be connected to any crystal controlled and noise free TTL source.

The Receiver synchronizes its internal clock with the incoming signal and recovers data

and clock for use by the receiving host system.

In the process of sending high speed data over typical serial links, the data may be

affected by noise from various sources. The PLL in the Receiver removes this noise and

delivers a synchronized clock to the Receiver logic and to the host system. However,

some of the noise may feed through the PLL and appear on the CLK output. The CLK

output can jitter as much as 2 ns when recovering data from a noisy link. This will not

typically affect normal logic functions, and can be ignored. If the Receiver must realign

its byte boundary, it will stretch CLK to the new alignment position and thus protect the

host logic from shortened CLK cycles.

These noise and phase jumps make the Receiver CLK output undesirable for use as a

Transmitter frequency source.

For systems that MUST use synchronized clocks (for example to avoid FIFO re-timing

logic) it is possible to filter the Receiver CLK output and make an adequate reference for

the Transmitter.

There are two basic approaches to provide this filter. The first is to use a crystal filter

(Figure 12). When placed between the Receiver CLK and Transmitter Xl, the crystal

filter can be effective in attenuating system jitter to levels nearly comparable to crystal

controlled reference clock levels. By the nature of a crystal filter, as the frequency of the

crystal used in the filter and the data rate frequency vary, the phase of the output varies.

This will make the filter seem to have a variable delay (+ or -) which must be accommo-

dated by the users logic.

The second method is to use a PLL tracking filter (Figure 13). The jitter attenuation

through the PLL is less than that through the crystal filter because the PLL has a

bandwidth several orders of magnitude larger. The PLL provides a solution whose

merits lie between the simplicity of the crystal filter and the need for tight crystal tracking

and matching. The PLL filter is relatively straight forward. Attention to proper grounding

and board layout should be followed. The PLL filter is more tolerant of component and

environmental variations than the crystal filter.

AM7968-125JC Datenblatt(PDF) 109 Page - Advanced Micro Devices