Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

Preview PDF HTML

WM8739LEDS Datenblatt(PDF) 8 Page - Wolfson Microelectronics plc

Teilenummer WM8739LEDS
Bauteilbeschribung  STEREO AUDIO ADC
PDF  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8739LEDS Datenblatt(HTML) 8 Page - Wolfson Microelectronics plc

Back Button WM8739LEDS Datasheet HTML 4Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 5Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 6Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 7Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 8Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 9Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 10Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 11Page - Wolfson Microelectronics plc WM8739LEDS Datasheet HTML 12Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 35 page
background image
WM8739 / WM8739L
Advanced Information
AI Rev 2.2 September 2001
8
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay
from BCLK falling edge
tDL
010
ns
ADCDAT propagation delay
from BCLK falling edge
tDDA
010
ns
BCLK
ADCDAT
ADCLRC
WM8739
ADC
DSP
ENCODER
Figure 4 Slave Mode Connection
BCLK
ADCLRC
t
BCH
t
BCL
t
BCY
ADCDAT
t
LRSU
t
LRH
t
DD
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
ADCLRC set-up time to
BCLK rising edge
tLRSU
10
ns
ADCLRC hold time from
BCLK rising edge
tLRH
10
ns
ADCDAT propagation delay
from BCLK falling edge
tDD
010
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com