WM8739 / WM8739L

Advanced Information

AI Rev 2.2 September 2001

18

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FORMAT[1:0]

10

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data

packed words

10 = I

justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

10

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

4

LRP

0

DSP mode A/B select (in DSP mode

only)

1 = MSB is available on 2nd BCLK

rising edge after LRC rising edge

0 = MSB is available on 1st BCLK

rising edge after LRC rising edge

0000111

Digital Audio

Interface Format

6

MS

0

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

Table 5 Digital Audio Interface Control

Note:

Right justified 32 bit mode is not supported, but if selected, will put the WM8739 into 24 bit right

justified mode.

MASTER AND SLAVE MODE OPERATION

The WM8739 can be configured as either a master or slave mode device. As a master mode device

the WM8739 controls sequencing of the data and clocks on the digital audio interface. As a slave

device the WM8739 responds with data to the clocks it receives over the digital audio interface. The

mode is set with the MS bit of the control register as shown in Table 6.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000111

Digital Audio

Interface

Format

6

MS

0

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

Table 6 Programming Master/Slave Modes

As a master mode device the WM8739 controls the sequencing of data transfer (ADCDAT) and

output of clocks (BCLK, ADCLRC) over the digital audio interface. It uses the timing generated from

either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This

is illustrated in Figure 17. ADCDAT is always an output from the WM8739 independent of master or

slave mode.