WM8739LEDS datasheet(21/35 Pages) WOLFSON

21 / 35 page

WM8739 / WM8739L

Advanced Information

AI Rev 2.2 September 2001

Example scenarios are:

with a requirement that the ADC data rate is 8kHz, then choosing MCLK = 12.288MHz the

device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC

output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6)

with a requirement that ADC data rate is 8kHz, then choosing MCLK = 16.9344MHz the device

is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 0, SR0 = 1. The ADC will no

longer output data at exactly 8.000KHz, instead it will be 8.018kHz (derived from

16.9344MHz/384 x 2/11). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio

data and (importantly) the user must ensure that the data across the digital interface is correctly

synchronised at the 8.018kHz rate.

The exact sample rates achieved are defined by the relationships in Table 9.

ACTUAL SAMPLING RATE

BOSR=0

(256fs)

BOSR=1

(384fs)

TARGET

SAMPLING

RATE

MCLK=12.288

MCLK=11.2896

MCLK=18.432

MCLK=16.9344

kHz

8.018

12.288MHz/256 x 1/6

11.2896MHz/256 x 2/11

18.432MHz/384 x 1/6

16.9344MHz/384 x 2/11

12.288MHz/256 x 2/3

not available

18.432MHz/384x 2/3

not available

44.1

not available

11.2896MHz/256

not available

16.9344MHz /384

12.288MHz/256

not available

18.432MHz/384

not available

88.2

not available

11.2896MHz/384 x 2

not available

16.9344MHz /384 x 2

12.288MHz/256 x 2

not available

18.432MHz/384 x 2

not available

Table 9 Normal Mode Actual Sample Rates

128/192fs NORMAL MODE

The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the

WM8739 is also capable of being clocked from a 128/192fs MCLK for application over limited

sampling rates as shown in the table below.

SAMPLING

RATE

MCLK

FREQUENCY

SAMPLE

RATE

DIGITAL

FILTER

TYPE

kHz

MHz

BOSR

SR3

SR2

SR1

SR0

6.144

9.216

5.6448

44.1

8.4672

Table 10 128/192fs Normal Mode Sample Rate Look-up Table

512/768fs NORMAL MODE

512fs and 768fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to

the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384fs internally and the

device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 4 for

software control.

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