LAN9115 datasheet(22/114 Pages) MICROCHIP

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LAN9115

DS00002269A-page 22

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The Filter i command register controls Filter i operation. Table 3-4 shows the Filter I command register.

The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined

by Filter i. Table 3-5 describes the Filter i Offset bit fields.

The Filter i CRC-16 register contains the CRC-16 result of the frame that should pass Filter i.

Table 3-6 describes the Filter i CRC-16 bit fields.

3.5.1

MAGIC PACKET DETECTION

Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”, places the

LAN9115 MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detection

logic within the MAC examines receive data for a Magic Packet. The LAN9115 can be programmed to notify the host of

the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power management event

signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set. When the host clears the

MPEN bit the LAN9115 will resume normal receive operation. Please refer to Section 5.4.12, "WUCSR—Wake-up Con-

trol and Status Register," on page 87 for additional information on this register.

In Magic Packet mode, the Power Management Logic constantly monitors each frame addressed to the node for a spe-

cific Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic

Packet requirement. The Power Management Logic checks each received frame for the pattern 48h

FF_FF_FF_FF_FF_FF after the destination and source address field.

TABLE 3-3:

FILTER I BYTE MASK BIT DEFINITIONS

Filter i Byte Mask Description

Field

Description

Must be zero (0)

30:0

Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset

+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.

TABLE 3-4:

FILTER I COMMAND BIT DEFINITIONS

Filter i Commands

Field

Description

Address Type: Defines the destination address type of the pattern. When bit is set, the pattern

applies

only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.

2:1

RESERVED

Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.

TABLE 3-5:

FILTER I OFFSET BIT DEFINITIONS

Filter i Offset Description

Field

Description

7:0

Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame

recognition. The minimum value of this field must be 12 since there should be no CRC check for the

destination address and the source address fields. The MAC checks the first offset byte of the frame

for CRC and checks to determine whether the frame is a wake-up frame. Offset 0 is the first byte of

the incoming frame's destination address.

TABLE 3-6:

FILTER I CRC-16 BIT DEFINITIONS

Filter i CRC-16 Description

Field

Description

15:0

Pattern CRC-16: This field contains the 16-bit CRC value from the pattern and the byte mask

programmed to the wake-up filter register Function. This value is compared against the CRC

calculated on the incoming frame, and a match indicates the reception of a wakeup frame.

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