LAN9115 datasheet(99/114 Pages) MICROCHIP

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DS00002269A-page 99

LAN9115

6.5

RX Data FIFO Direct PIO Burst Reads

In this mode the upper address inputs are not decoded, and any burst read of the LAN9115 will read the RX Data FIFO.

This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting

the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its

address when accessing the LAN9115. Timing is identical to a PIO Burst Read, and the FIFO_SEL signal has the same

timing characteristics as the address lines. In this mode, performance is improved by allowing an unlimited number of

back-to-back DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip

Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must remain high for the

period specified.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

FIGURE 6-3:

RX DATA FIFO DIRECT PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-5:

RX DATA FIFO DIRECT PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

165

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends

when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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